VLSI realization of 2D HDTV subband filter-banks with on-chip line memories and FIFOs

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

Authors

  • K. Grüger
  • M. Winzker
  • W. Gehrke
  • P. Pirsch

Research Organisations

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Details

Original languageEnglish
Title of host publicationESSCIRC 1992
Subtitle of host publication18th European Solid-State Circuits Conference, Proceedings
PublisherIEEE Computer Society
Pages319-322
Number of pages4
ISBN (electronic)8798423207
Publication statusPublished - 1992
Event18th European Solid-State Circuits Conference, ESSCIRC 1992 - Copenhagen, Denmark
Duration: 21 Sept 1992 → 23 Sept 1992

Publication series

NameEuropean Solid-State Circuits Conference
Volume1992-September
ISSN (Print)1930-8833

Abstract

Subband coding is frequently proposed for source coding of HDTV. Key components for the compact realization of subband codecs are VLSI filterbanks for analysis and synthesis filtering. Avoiding programmability the development and application of dedicated subband filterbanks can significantly reduce hardware expense. For 2D Quadrature Mirror Filterbanks with 14x 10 taps, a chip set with on-chip line memories and synchronous FIFOs has been developed using a 1.2jim-CMOS technology. Only two identical ICs each with about 450,000 transistors and a chip area of 92mm2 are necessary for one filterbank. The implementation is adapted to the systems parameters of interlaced scanning but the architecture can easily be extended to the processing of future progressive HDTV.

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Cite this

VLSI realization of 2D HDTV subband filter-banks with on-chip line memories and FIFOs. / Grüger, K.; Winzker, M.; Gehrke, W. et al.
ESSCIRC 1992 : 18th European Solid-State Circuits Conference, Proceedings. IEEE Computer Society, 1992. p. 319-322 5468153 (European Solid-State Circuits Conference; Vol. 1992-September).

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

Grüger, K, Winzker, M, Gehrke, W & Pirsch, P 1992, VLSI realization of 2D HDTV subband filter-banks with on-chip line memories and FIFOs. in ESSCIRC 1992 : 18th European Solid-State Circuits Conference, Proceedings., 5468153, European Solid-State Circuits Conference, vol. 1992-September, IEEE Computer Society, pp. 319-322, 18th European Solid-State Circuits Conference, ESSCIRC 1992, Copenhagen, Denmark, 21 Sept 1992. https://doi.org/10.1109/ESSCIRC.1992.5468153
Grüger, K., Winzker, M., Gehrke, W., & Pirsch, P. (1992). VLSI realization of 2D HDTV subband filter-banks with on-chip line memories and FIFOs. In ESSCIRC 1992 : 18th European Solid-State Circuits Conference, Proceedings (pp. 319-322). Article 5468153 (European Solid-State Circuits Conference; Vol. 1992-September). IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.1992.5468153
Grüger K, Winzker M, Gehrke W, Pirsch P. VLSI realization of 2D HDTV subband filter-banks with on-chip line memories and FIFOs. In ESSCIRC 1992 : 18th European Solid-State Circuits Conference, Proceedings. IEEE Computer Society. 1992. p. 319-322. 5468153. (European Solid-State Circuits Conference). doi: 10.1109/ESSCIRC.1992.5468153
Grüger, K. ; Winzker, M. ; Gehrke, W. et al. / VLSI realization of 2D HDTV subband filter-banks with on-chip line memories and FIFOs. ESSCIRC 1992 : 18th European Solid-State Circuits Conference, Proceedings. IEEE Computer Society, 1992. pp. 319-322 (European Solid-State Circuits Conference).
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title = "VLSI realization of 2D HDTV subband filter-banks with on-chip line memories and FIFOs",
abstract = "Subband coding is frequently proposed for source coding of HDTV. Key components for the compact realization of subband codecs are VLSI filterbanks for analysis and synthesis filtering. Avoiding programmability the development and application of dedicated subband filterbanks can significantly reduce hardware expense. For 2D Quadrature Mirror Filterbanks with 14x 10 taps, a chip set with on-chip line memories and synchronous FIFOs has been developed using a 1.2jim-CMOS technology. Only two identical ICs each with about 450,000 transistors and a chip area of 92mm2 are necessary for one filterbank. The implementation is adapted to the systems parameters of interlaced scanning but the architecture can easily be extended to the processing of future progressive HDTV.",
author = "K. Gr{\"u}ger and M. Winzker and W. Gehrke and P. Pirsch",
note = "Funding Information: 6. CONCLUSION AchipsetforHDTVsubbandfilteringhasbeendeveloped.Closeinteractionduringthedevelopmentofthealgo¬ rithm foranalysis synthesis filtering and the hardware architecture lead to a compactrealization. All in advance known properties of the algorithm are utilized. In particular the application of a Quadrature Mirror Filter with fixed filter coefficients was advantageous. On-chip memories provide the high data access rate needed between vertical memory and arithmetic. The implemented chip realization showed the feasibility of the approach. Usinga dedicated hardware architecture can lead topowerful compact implementations.Thechip set has been developed and tested for interlaced scanned HDTV signals, but the proposed architecture can even process 144MHz sampled progressive HDTV pictures with available CMOS technology. 7. ACKNOWLEDGMENTS Thisworkhasbeen supported by the Research Institute of the Deutsche Bundespost Telekom which is gratefully acknowledged. They provided help during chip layout. also valuable 8. REFERENCESthe [1]D.LeGall,H.Gaggioni,C.-T.Chen,'TransmissionofHDTVsignalsunder140Mbits/susingasub-banddecomposition and discrete cosine transform coding.{"} 2. Int Workshop on Signal Processing of HDTV. L'Aquila, 1988. [2] U. Pestel, B. Schmale, {"}Design of an HDTV subband codec considering CMOS-VLSI constraints,{"} Visual Communications andImageProcessing'90,MuratKunt,Editor,SP.,1990,Vol.1360,pp.587-597. [3] T.-C. Chen, P. E. Fleischer, S .-M. Lei, {"}A subband scheme for advanced TV coding in BISDN applications,{"} in Signal Proces¬ U.sing of HDTVK. II, ed. by L. Chiariglione,ofHDTV SubbandElsevier,Filterbanks1990, pp. 553-560. in IEEE Trans, [4] Pestel, Griiger, {"}Design Considering VLSIImplementation Constraints,{"} on Circuits andSystems for VideoTechnology, Vol. 1, No. 1, March 1991, pp. 14-21. [5] A. V.Oppenheim,R.W. Sch{\"a}fer, Digital Signal Processing. Prentice-Hall, 1975, pp. 155-165. [6] M. J. T. Smith, T. P. Barnwell, {"}Exact reconstruction techniques for tree-structured subband coders{"}, IEEE Trans, on acous¬ tics, speech and signal processing. Vol. ASSP-34, No. 3, June 1986, pp. 434-441. [7] CCIR, {"}The Present State ofHigh-Definition Television. Part5.1.2,{"}CCIR Report 801-3, January 1990. ; 18th European Solid-State Circuits Conference, ESSCIRC 1992 ; Conference date: 21-09-1992 Through 23-09-1992",
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T1 - VLSI realization of 2D HDTV subband filter-banks with on-chip line memories and FIFOs

AU - Grüger, K.

AU - Winzker, M.

AU - Gehrke, W.

AU - Pirsch, P.

N1 - Funding Information: 6. CONCLUSION AchipsetforHDTVsubbandfilteringhasbeendeveloped.Closeinteractionduringthedevelopmentofthealgo¬ rithm foranalysis synthesis filtering and the hardware architecture lead to a compactrealization. All in advance known properties of the algorithm are utilized. In particular the application of a Quadrature Mirror Filter with fixed filter coefficients was advantageous. On-chip memories provide the high data access rate needed between vertical memory and arithmetic. The implemented chip realization showed the feasibility of the approach. Usinga dedicated hardware architecture can lead topowerful compact implementations.Thechip set has been developed and tested for interlaced scanned HDTV signals, but the proposed architecture can even process 144MHz sampled progressive HDTV pictures with available CMOS technology. 7. ACKNOWLEDGMENTS Thisworkhasbeen supported by the Research Institute of the Deutsche Bundespost Telekom which is gratefully acknowledged. They provided help during chip layout. also valuable 8. REFERENCESthe [1]D.LeGall,H.Gaggioni,C.-T.Chen,'TransmissionofHDTVsignalsunder140Mbits/susingasub-banddecomposition and discrete cosine transform coding." 2. Int Workshop on Signal Processing of HDTV. L'Aquila, 1988. [2] U. Pestel, B. Schmale, "Design of an HDTV subband codec considering CMOS-VLSI constraints," Visual Communications andImageProcessing'90,MuratKunt,Editor,SP.,1990,Vol.1360,pp.587-597. [3] T.-C. Chen, P. E. Fleischer, S .-M. Lei, "A subband scheme for advanced TV coding in BISDN applications," in Signal Proces¬ U.sing of HDTVK. II, ed. by L. Chiariglione,ofHDTV SubbandElsevier,Filterbanks1990, pp. 553-560. in IEEE Trans, [4] Pestel, Griiger, "Design Considering VLSIImplementation Constraints," on Circuits andSystems for VideoTechnology, Vol. 1, No. 1, March 1991, pp. 14-21. [5] A. V.Oppenheim,R.W. Schäfer, Digital Signal Processing. Prentice-Hall, 1975, pp. 155-165. [6] M. J. T. Smith, T. P. Barnwell, "Exact reconstruction techniques for tree-structured subband coders", IEEE Trans, on acous¬ tics, speech and signal processing. Vol. ASSP-34, No. 3, June 1986, pp. 434-441. [7] CCIR, "The Present State ofHigh-Definition Television. Part5.1.2,"CCIR Report 801-3, January 1990.

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AB - Subband coding is frequently proposed for source coding of HDTV. Key components for the compact realization of subband codecs are VLSI filterbanks for analysis and synthesis filtering. Avoiding programmability the development and application of dedicated subband filterbanks can significantly reduce hardware expense. For 2D Quadrature Mirror Filterbanks with 14x 10 taps, a chip set with on-chip line memories and synchronous FIFOs has been developed using a 1.2jim-CMOS technology. Only two identical ICs each with about 450,000 transistors and a chip area of 92mm2 are necessary for one filterbank. The implementation is adapted to the systems parameters of interlaced scanning but the architecture can easily be extended to the processing of future progressive HDTV.

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BT - ESSCIRC 1992

PB - IEEE Computer Society

T2 - 18th European Solid-State Circuits Conference, ESSCIRC 1992

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