Details
| Original language | English |
|---|---|
| Pages (from-to) | 1354-1361 |
| Number of pages | 8 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 28 |
| Issue number | 12 |
| Publication status | Published - Dec 1993 |
Abstract
A chip set for 2D subband filtering of HDTV signals has been designed, fabricated and successfully tested. The two chips perform 10 * 14 quadrature mirror filtering for analysis filtering at the coder and synthesis filtering at the decoder. In order to achieve a very compact realization, the architectures utilize all a priori known properties of the filter algorithm. A 2D polyphase filter structure reduces the processing clock rate from the 72-MHz sampling rate to a moderate 18 MHz. The memory for vertical filtering is realized by on-chip parallel shift registers with multiphase clocking. A small silicon area for the filter arithmetic is achieved by application of carry save adder trees with fixed filter coefficients represented by canonical signed digits. A complete filterbank for luminance and chrominance signals consists of four identical chips, each with 450000 transistors on 92 mm2.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: IEEE Journal of Solid-State Circuits, Vol. 28, No. 12, 12.1993, p. 1354-1361.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - VLSI Chip Set for 2D HDTV Subband Filtering with On-Chip Line Memories
AU - Winzker, Marco
AU - Grüger, Klaus
AU - Gehrke, Winfried
AU - Pirsch, Peter
N1 - Funding Information: This work has been supported by the Research Institute of the Deutsche Bundespost Telekom which is gratefully acknowledged. They also provided valuable help during the chip layout.
PY - 1993/12
Y1 - 1993/12
N2 - A chip set for 2D subband filtering of HDTV signals has been designed, fabricated and successfully tested. The two chips perform 10 * 14 quadrature mirror filtering for analysis filtering at the coder and synthesis filtering at the decoder. In order to achieve a very compact realization, the architectures utilize all a priori known properties of the filter algorithm. A 2D polyphase filter structure reduces the processing clock rate from the 72-MHz sampling rate to a moderate 18 MHz. The memory for vertical filtering is realized by on-chip parallel shift registers with multiphase clocking. A small silicon area for the filter arithmetic is achieved by application of carry save adder trees with fixed filter coefficients represented by canonical signed digits. A complete filterbank for luminance and chrominance signals consists of four identical chips, each with 450000 transistors on 92 mm2.
AB - A chip set for 2D subband filtering of HDTV signals has been designed, fabricated and successfully tested. The two chips perform 10 * 14 quadrature mirror filtering for analysis filtering at the coder and synthesis filtering at the decoder. In order to achieve a very compact realization, the architectures utilize all a priori known properties of the filter algorithm. A 2D polyphase filter structure reduces the processing clock rate from the 72-MHz sampling rate to a moderate 18 MHz. The memory for vertical filtering is realized by on-chip parallel shift registers with multiphase clocking. A small silicon area for the filter arithmetic is achieved by application of carry save adder trees with fixed filter coefficients represented by canonical signed digits. A complete filterbank for luminance and chrominance signals consists of four identical chips, each with 450000 transistors on 92 mm2.
UR - http://www.scopus.com/inward/record.url?scp=0027807014&partnerID=8YFLogxK
U2 - 10.1109/4.262010
DO - 10.1109/4.262010
M3 - Article
AN - SCOPUS:0027807014
VL - 28
SP - 1354
EP - 1361
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 12
ER -