Details
| Original language | English |
|---|---|
| Pages (from-to) | 110-120 |
| Number of pages | 11 |
| Journal | Annales Des Télécommunications |
| Volume | 46 |
| Issue number | 1-2 |
| Publication status | Published - Jan 1991 |
Abstract
VLSI architectures of filterbanks necessary for an HDTV subband codec have been investigated. Different techniques have been combined in order to achieve a compact realization. The application of special QMF structures results in a further reduction of hardware expense. High clocking rates are handled using two dimensional polyphase filterbanks in combination with pipelining and parallel processing. An architecture suitable for one-chip implementation of a 10 x 14 tap QM filterbank has been developed.
Keywords
- Codec, High definition television, Image coding, Polyphase circuit, Quadrature mirror filter, Subband decomposition, VLSI circuit
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: Annales Des Télécommunications, Vol. 46, No. 1-2, 01.1991, p. 110-120.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - VLSI architectures of filterbanks for subband coding of hdtv signals
AU - Grüger, Klaus
AU - Pirsch, Peter
AU - Winzker, Marco
PY - 1991/1
Y1 - 1991/1
N2 - VLSI architectures of filterbanks necessary for an HDTV subband codec have been investigated. Different techniques have been combined in order to achieve a compact realization. The application of special QMF structures results in a further reduction of hardware expense. High clocking rates are handled using two dimensional polyphase filterbanks in combination with pipelining and parallel processing. An architecture suitable for one-chip implementation of a 10 x 14 tap QM filterbank has been developed.
AB - VLSI architectures of filterbanks necessary for an HDTV subband codec have been investigated. Different techniques have been combined in order to achieve a compact realization. The application of special QMF structures results in a further reduction of hardware expense. High clocking rates are handled using two dimensional polyphase filterbanks in combination with pipelining and parallel processing. An architecture suitable for one-chip implementation of a 10 x 14 tap QM filterbank has been developed.
KW - Codec
KW - High definition television
KW - Image coding
KW - Polyphase circuit
KW - Quadrature mirror filter
KW - Subband decomposition
KW - VLSI circuit
UR - http://www.scopus.com/inward/record.url?scp=0025786224&partnerID=8YFLogxK
U2 - 10.1007/BF02995441
DO - 10.1007/BF02995441
M3 - Article
AN - SCOPUS:0025786224
VL - 46
SP - 110
EP - 120
JO - Annales Des Télécommunications
JF - Annales Des Télécommunications
SN - 0003-4347
IS - 1-2
ER -