Details
| Original language | English |
|---|---|
| Pages (from-to) | 6-10 |
| Number of pages | 5 |
| Journal | IEE Conference Publication |
| Issue number | 410 |
| Publication status | Published - Feb 1995 |
| Event | 5th International Conference on Image Processing and its Applications - Edinburgh, UK Duration: 4 Jul 1995 → 6 Jul 1995 |
Abstract
The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO, focussing on programmable architectures. Programmable video signal processors are classified and specified as homogeneous and heterogeneous processor architectures. Heterogeneous processors outperform homogeneous processors due to adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogeneous processors incorporate dedicated modules for high performance subtasks of high regularity like DCT and block matching. By normalization to a fictive 1.0 micron CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: IEE Conference Publication, No. 410, 02.1995, p. 6-10.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - VLSI architectures for video signal processing
AU - Pirsch, Peter
AU - Gehrke, Winfried
PY - 1995/2
Y1 - 1995/2
N2 - The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO, focussing on programmable architectures. Programmable video signal processors are classified and specified as homogeneous and heterogeneous processor architectures. Heterogeneous processors outperform homogeneous processors due to adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogeneous processors incorporate dedicated modules for high performance subtasks of high regularity like DCT and block matching. By normalization to a fictive 1.0 micron CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency.
AB - The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO, focussing on programmable architectures. Programmable video signal processors are classified and specified as homogeneous and heterogeneous processor architectures. Heterogeneous processors outperform homogeneous processors due to adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogeneous processors incorporate dedicated modules for high performance subtasks of high regularity like DCT and block matching. By normalization to a fictive 1.0 micron CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency.
UR - http://www.scopus.com/inward/record.url?scp=0029214130&partnerID=8YFLogxK
U2 - 10.1049/cp:19950609
DO - 10.1049/cp:19950609
M3 - Conference article
AN - SCOPUS:0029214130
SP - 6
EP - 10
JO - IEE Conference Publication
JF - IEE Conference Publication
SN - 0537-9989
IS - 410
T2 - 5th International Conference on Image Processing and its Applications
Y2 - 4 July 1995 through 6 July 1995
ER -