Details
| Original language | English |
|---|---|
| Pages (from-to) | 220-246 |
| Number of pages | 27 |
| Journal | Proceedings of the IEEE |
| Volume | 83 |
| Issue number | 2 |
| Publication status | Published - Feb 1995 |
Abstract
The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures for DCT and block matching will be evaluated. Also dedicated decoder chips are included. Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 μm CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: Proceedings of the IEEE, Vol. 83, No. 2, 02.1995, p. 220-246.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - VLSI Architectures for Video Compression
T2 - A Survey
AU - Pirsch, Peter
AU - Gehrke, Winfried
AU - Demassieux, Nicolas
PY - 1995/2
Y1 - 1995/2
N2 - The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures for DCT and block matching will be evaluated. Also dedicated decoder chips are included. Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 μm CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency.
AB - The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures for DCT and block matching will be evaluated. Also dedicated decoder chips are included. Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 μm CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency.
UR - http://www.scopus.com/inward/record.url?scp=0029244586&partnerID=8YFLogxK
U2 - 10.1109/5.364465
DO - 10.1109/5.364465
M3 - Article
AN - SCOPUS:0029244586
VL - 83
SP - 220
EP - 246
JO - Proceedings of the IEEE
JF - Proceedings of the IEEE
SN - 0018-9219
IS - 2
ER -