Details
| Original language | English |
|---|---|
| Pages (from-to) | 45-48 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| Publication status | Published - 1990 |
| Event | 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA Duration: 1 May 1990 → 3 May 1990 |
Abstract
An application-specific multiprocessor system is investigated for real-time implementation of the hierarchical block matching algorithm. The proposed architecture is based on parallel processing units and local memories which are globally preloaded via a common bus. The performance is estimated for the data transfer and the parallel computation time schedule.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 1, 1990, p. 45-48.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - VLSI architectures for hierarchical block matching algorithms
AU - Komarek, T.
AU - Pirsch, P.
PY - 1990
Y1 - 1990
N2 - An application-specific multiprocessor system is investigated for real-time implementation of the hierarchical block matching algorithm. The proposed architecture is based on parallel processing units and local memories which are globally preloaded via a common bus. The performance is estimated for the data transfer and the parallel computation time schedule.
AB - An application-specific multiprocessor system is investigated for real-time implementation of the hierarchical block matching algorithm. The proposed architecture is based on parallel processing units and local memories which are globally preloaded via a common bus. The performance is estimated for the data transfer and the parallel computation time schedule.
UR - http://www.scopus.com/inward/record.url?scp=0025596048&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0025596048
VL - 1
SP - 45
EP - 48
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
T2 - 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4)
Y2 - 1 May 1990 through 3 May 1990
ER -