Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the International Workshop on Rapid System Prototyping |
| Editors | J. Becker |
| Pages | 170-175 |
| Number of pages | 6 |
| Publication status | Published - 1998 |
| Event | 1998 9th IEEE International Workshop on Rapid System Prototyping - Leuven, Belgium Duration: 3 Jun 1998 → 5 Jun 1998 |
Publication series
| Name | Proceedings of the International Workshop on Rapid System Prototyping |
|---|---|
| ISSN (Print) | 1074-6005 |
Abstract
We present a real-time emulation system for complete video processing schemes. Our emulation system is based on a commercial FPGA emulator and related software. To meet real-time constraints, we have extended this emulation environment by dedicated video interfaces, efficient flexible FPGA macros, and a modified design flow. The feasibility of this methodology is shown for a two-dimensional discrete cosine transform, resulting in a reduction of approximately 58% in terms of FPGA resources. The emulation frequency improves by 33%. Furthermore, by emulating different coefficient word widths and subjective evaluation of image quality, it could be shown, that a word width of 10 bits is sufficient for our design.
ASJC Scopus subject areas
- Computer Science(all)
- General Computer Science
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Proceedings of the International Workshop on Rapid System Prototyping. ed. / J. Becker. 1998. p. 170-175 (Proceedings of the International Workshop on Rapid System Prototyping).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Video and image processing emulation system VIPES
AU - Kropp, H.
AU - Reuter, C.
AU - Pirsch, P.
PY - 1998
Y1 - 1998
N2 - We present a real-time emulation system for complete video processing schemes. Our emulation system is based on a commercial FPGA emulator and related software. To meet real-time constraints, we have extended this emulation environment by dedicated video interfaces, efficient flexible FPGA macros, and a modified design flow. The feasibility of this methodology is shown for a two-dimensional discrete cosine transform, resulting in a reduction of approximately 58% in terms of FPGA resources. The emulation frequency improves by 33%. Furthermore, by emulating different coefficient word widths and subjective evaluation of image quality, it could be shown, that a word width of 10 bits is sufficient for our design.
AB - We present a real-time emulation system for complete video processing schemes. Our emulation system is based on a commercial FPGA emulator and related software. To meet real-time constraints, we have extended this emulation environment by dedicated video interfaces, efficient flexible FPGA macros, and a modified design flow. The feasibility of this methodology is shown for a two-dimensional discrete cosine transform, resulting in a reduction of approximately 58% in terms of FPGA resources. The emulation frequency improves by 33%. Furthermore, by emulating different coefficient word widths and subjective evaluation of image quality, it could be shown, that a word width of 10 bits is sufficient for our design.
UR - http://www.scopus.com/inward/record.url?scp=0031682860&partnerID=8YFLogxK
U2 - 10.1109/IWRSP.1998.676687
DO - 10.1109/IWRSP.1998.676687
M3 - Conference contribution
AN - SCOPUS:0031682860
SN - 0818684798
T3 - Proceedings of the International Workshop on Rapid System Prototyping
SP - 170
EP - 175
BT - Proceedings of the International Workshop on Rapid System Prototyping
A2 - Becker, J.
T2 - 1998 9th IEEE International Workshop on Rapid System Prototyping
Y2 - 3 June 1998 through 5 June 1998
ER -