Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings of SPIE |
| Subtitle of host publication | The International Society for Optical Engineering |
| Pages | 758-777 |
| Number of pages | 20 |
| Edition | 2/- |
| Publication status | Published - 1995 |
| Event | Visual Communications and Image Processing '95 - Taipei, Taiwan Duration: 24 May 1995 → 26 May 1995 |
Publication series
| Name | SPIE - The International Society for Optical Engineering |
|---|---|
| Number | 2/- |
| Volume | 2501 |
| ISSN (Print) | 0277-786X |
Abstract
The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO, focussing on programmable architectures. Programmable video signal processors are classified and specified as homogeneous and heterogeneous processor architectures. Architectures are presented for reported design examples for the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 micron CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicated a figure of merit for silicon efficiency.
ASJC Scopus subject areas
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Physics and Astronomy(all)
- Condensed Matter Physics
- Computer Science(all)
- Computer Science Applications
- Mathematics(all)
- Applied Mathematics
- Engineering(all)
- Electrical and Electronic Engineering
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Proceedings of SPIE : The International Society for Optical Engineering. 2/-. ed. 1995. p. 758-777 (SPIE - The International Society for Optical Engineering; Vol. 2501 , No. 2/-).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Very large scale integration (VLSI) architectures for video signal processing
AU - Pirsch, Peter
AU - Gehrke, Winfried
PY - 1995
Y1 - 1995
N2 - The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO, focussing on programmable architectures. Programmable video signal processors are classified and specified as homogeneous and heterogeneous processor architectures. Architectures are presented for reported design examples for the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 micron CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicated a figure of merit for silicon efficiency.
AB - The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO, focussing on programmable architectures. Programmable video signal processors are classified and specified as homogeneous and heterogeneous processor architectures. Architectures are presented for reported design examples for the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 micron CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicated a figure of merit for silicon efficiency.
UR - http://www.scopus.com/inward/record.url?scp=0029213598&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0029213598
SN - 0819418587
T3 - SPIE - The International Society for Optical Engineering
SP - 758
EP - 777
BT - Proceedings of SPIE
T2 - Visual Communications and Image Processing '95
Y2 - 24 May 1995 through 26 May 1995
ER -