Details
| Original language | English |
|---|---|
| Article number | 014002 |
| Journal | Semiconductor Science and Technology |
| Volume | 36 |
| Issue number | 1 |
| Early online date | 29 Oct 2020 |
| Publication status | Published - Jan 2021 |
| Externally published | Yes |
Abstract
This paper demonstrates the first vertical field-effect transistor based on gallium nitride (GaN) fin structures with an inverted p-doped channel layer. A top-down hybrid etching approach combining inductively coupled plasma reactive ion etching and KOH-based wet etching was applied to fabricate regular fields of GaN fins with smooth a-plane sidewalls. The obtained morphologies are explained using a cavity step-flow model. A 3D processing scheme has been developed and evaluated via focussed ion beam cross-sections. The top-down approach allows the introduction of arbitrary doping profiles along the channel without regrowth, enabling the modulation of the channel properties and thus increasing the flexibility of the device concept. Here, a vertical npn-doping profile was used to achieve normally-off operation with an increased threshold voltage as high as 2.65 V. The p-doped region and the 3D gate wrapped around the sidewalls create a very narrow vertical electron channel close to the interface between dielectric and semiconductor, resulting in good electrostatic gate control, low leakage currents through the inner fin core and high sensitivity to the interface between GaN and gate oxide. Hydrodynamic transport simulations were carried out and show good agreement with the performed current-voltage and capacitance-voltage measurements. The simulation indicates a reduced channel mobility which we attribute to interface scattering being particularly relevant in narrow channels. We also demonstrate the existence of oxide and interface traps with an estimated sheet density of 3.2 × 1012 cm-2 related to the Al2O3 gate dielectric causing an increased subthreshold swing. Thus, improving the interface quality is essential to reach the full potential of the presented vertical 3D transistor concept.
Keywords
- field-effect transistor, gallium nitride, nanostructures, vertical electronics
ASJC Scopus subject areas
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Physics and Astronomy(all)
- Condensed Matter Physics
- Engineering(all)
- Electrical and Electronic Engineering
- Materials Science(all)
- Materials Chemistry
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In: Semiconductor Science and Technology, Vol. 36, No. 1, 014002, 01.2021.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Vertical 3D gallium nitride field-effect transistors based on fin structures with inverted p-doped channel
AU - Strempel, Klaas
AU - Römer, Friedhard
AU - Yu, Feng
AU - Meneghini, Matteo
AU - Bakin, Andrey
AU - Wehmann, Hergo Heinrich
AU - Witzigmann, Bernd
AU - Waag, Andreas
N1 - Acknowledgments This work was funded by the Deutsche Forschungsgesellschaft (DFG, German Research Formation) within the project ‘3D Concepts for Gallium Nitride Electroncis’— 284575374 and under Germany’s Excellence Strategy—EXC- 2123 Quantum Frontiers—390837967. The authors thank I. Manglano Clavero and C. Margenfeld for wafer growth in the Epitaxy Competence Center (ec2), a joint venture by the Institute of Semiconductor Technology and OSRAM Opto Semiconductors. We gratefully acknowledge the technical assistance of Juliane Breitfelder, Diana Herz and Angelika Schmidt.
PY - 2021/1
Y1 - 2021/1
N2 - This paper demonstrates the first vertical field-effect transistor based on gallium nitride (GaN) fin structures with an inverted p-doped channel layer. A top-down hybrid etching approach combining inductively coupled plasma reactive ion etching and KOH-based wet etching was applied to fabricate regular fields of GaN fins with smooth a-plane sidewalls. The obtained morphologies are explained using a cavity step-flow model. A 3D processing scheme has been developed and evaluated via focussed ion beam cross-sections. The top-down approach allows the introduction of arbitrary doping profiles along the channel without regrowth, enabling the modulation of the channel properties and thus increasing the flexibility of the device concept. Here, a vertical npn-doping profile was used to achieve normally-off operation with an increased threshold voltage as high as 2.65 V. The p-doped region and the 3D gate wrapped around the sidewalls create a very narrow vertical electron channel close to the interface between dielectric and semiconductor, resulting in good electrostatic gate control, low leakage currents through the inner fin core and high sensitivity to the interface between GaN and gate oxide. Hydrodynamic transport simulations were carried out and show good agreement with the performed current-voltage and capacitance-voltage measurements. The simulation indicates a reduced channel mobility which we attribute to interface scattering being particularly relevant in narrow channels. We also demonstrate the existence of oxide and interface traps with an estimated sheet density of 3.2 × 1012 cm-2 related to the Al2O3 gate dielectric causing an increased subthreshold swing. Thus, improving the interface quality is essential to reach the full potential of the presented vertical 3D transistor concept.
AB - This paper demonstrates the first vertical field-effect transistor based on gallium nitride (GaN) fin structures with an inverted p-doped channel layer. A top-down hybrid etching approach combining inductively coupled plasma reactive ion etching and KOH-based wet etching was applied to fabricate regular fields of GaN fins with smooth a-plane sidewalls. The obtained morphologies are explained using a cavity step-flow model. A 3D processing scheme has been developed and evaluated via focussed ion beam cross-sections. The top-down approach allows the introduction of arbitrary doping profiles along the channel without regrowth, enabling the modulation of the channel properties and thus increasing the flexibility of the device concept. Here, a vertical npn-doping profile was used to achieve normally-off operation with an increased threshold voltage as high as 2.65 V. The p-doped region and the 3D gate wrapped around the sidewalls create a very narrow vertical electron channel close to the interface between dielectric and semiconductor, resulting in good electrostatic gate control, low leakage currents through the inner fin core and high sensitivity to the interface between GaN and gate oxide. Hydrodynamic transport simulations were carried out and show good agreement with the performed current-voltage and capacitance-voltage measurements. The simulation indicates a reduced channel mobility which we attribute to interface scattering being particularly relevant in narrow channels. We also demonstrate the existence of oxide and interface traps with an estimated sheet density of 3.2 × 1012 cm-2 related to the Al2O3 gate dielectric causing an increased subthreshold swing. Thus, improving the interface quality is essential to reach the full potential of the presented vertical 3D transistor concept.
KW - field-effect transistor
KW - gallium nitride
KW - nanostructures
KW - vertical electronics
UR - http://www.scopus.com/inward/record.url?scp=85097320175&partnerID=8YFLogxK
U2 - 10.1088/1361-6641/abc5ff
DO - 10.1088/1361-6641/abc5ff
M3 - Article
AN - SCOPUS:85097320175
VL - 36
JO - Semiconductor Science and Technology
JF - Semiconductor Science and Technology
SN - 0268-1242
IS - 1
M1 - 014002
ER -