Details
| Original language | English |
|---|---|
| Title of host publication | Architecture of Computing Systems |
| Subtitle of host publication | 36th International Conference, ARCS 2023, Athens, Greece, June 13–15, 2023, Proceedings |
| Editors | Georgios Goumas, Sven Tomforde, Jürgen Brehm, Stefan Wildermann, Thilo Pionteck |
| Publisher | Springer Science and Business Media Deutschland GmbH |
| Pages | 139-152 |
| Number of pages | 14 |
| ISBN (electronic) | 978-3-031-42785-5 |
| ISBN (print) | 9783031427848 |
| Publication status | Published - 26 Aug 2023 |
| Event | 36th International Conference on Architecture of Computing Systems, ARCS 2023 - Athens, Greece Duration: 13 Jun 2023 → 15 Jun 2023 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 13949 LNCS |
| ISSN (Print) | 0302-9743 |
| ISSN (electronic) | 1611-3349 |
Abstract
The Apple M1 ARM processors incorporate two memory consistency models: the conventional ARM weak memory ordering and the total store ordering (TSO) model from the x86 architecture employed by Apple’s x86 emulator, Rosetta 2. The presence of both memory ordering models on the same hardware enables us to thoroughly benchmark and compare their performance characteristics and worst-case workloads. In this paper, we assess the performance implications of TSO on the Apple M1 processor architecture. Based on various workloads, our findings indicate that TSO is, on average, 8.94% slower than ARM’s weaker memory ordering. Through synthetic benchmarks, we further explore the workloads that experience the most significant performance degradation due to TSO.
Keywords
- Apple M1, Memory Ordering, TSO
ASJC Scopus subject areas
- Mathematics(all)
- Theoretical Computer Science
- Computer Science(all)
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Architecture of Computing Systems: 36th International Conference, ARCS 2023, Athens, Greece, June 13–15, 2023, Proceedings. ed. / Georgios Goumas; Sven Tomforde; Jürgen Brehm; Stefan Wildermann; Thilo Pionteck. Springer Science and Business Media Deutschland GmbH, 2023. p. 139-152 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 13949 LNCS).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
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TY - GEN
T1 - TOSTING
T2 - 36th International Conference on Architecture of Computing Systems, ARCS 2023
AU - Wrenger, Lars
AU - Töllner, Dominik
AU - Lohmann, Daniel
PY - 2023/8/26
Y1 - 2023/8/26
N2 - The Apple M1 ARM processors incorporate two memory consistency models: the conventional ARM weak memory ordering and the total store ordering (TSO) model from the x86 architecture employed by Apple’s x86 emulator, Rosetta 2. The presence of both memory ordering models on the same hardware enables us to thoroughly benchmark and compare their performance characteristics and worst-case workloads. In this paper, we assess the performance implications of TSO on the Apple M1 processor architecture. Based on various workloads, our findings indicate that TSO is, on average, 8.94% slower than ARM’s weaker memory ordering. Through synthetic benchmarks, we further explore the workloads that experience the most significant performance degradation due to TSO.
AB - The Apple M1 ARM processors incorporate two memory consistency models: the conventional ARM weak memory ordering and the total store ordering (TSO) model from the x86 architecture employed by Apple’s x86 emulator, Rosetta 2. The presence of both memory ordering models on the same hardware enables us to thoroughly benchmark and compare their performance characteristics and worst-case workloads. In this paper, we assess the performance implications of TSO on the Apple M1 processor architecture. Based on various workloads, our findings indicate that TSO is, on average, 8.94% slower than ARM’s weaker memory ordering. Through synthetic benchmarks, we further explore the workloads that experience the most significant performance degradation due to TSO.
KW - Apple M1
KW - Memory Ordering
KW - TSO
UR - http://www.scopus.com/inward/record.url?scp=85171469703&partnerID=8YFLogxK
U2 - 10.1007/978-3-031-42785-5_10
DO - 10.1007/978-3-031-42785-5_10
M3 - Conference contribution
AN - SCOPUS:85171469703
SN - 9783031427848
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 139
EP - 152
BT - Architecture of Computing Systems
A2 - Goumas, Georgios
A2 - Tomforde, Sven
A2 - Brehm, Jürgen
A2 - Wildermann, Stefan
A2 - Pionteck, Thilo
PB - Springer Science and Business Media Deutschland GmbH
Y2 - 13 June 2023 through 15 June 2023
ER -