Details
| Original language | English |
|---|---|
| Pages | 120-125 |
| Number of pages | 6 |
| Publication status | Published - 1996 |
| Event | 1996 European Design Automation Conference with EURO-VHDL'96 and Exhibition - Geneva, Switzerland Duration: 16 Sept 1996 → 20 Sept 1996 |
Conference
| Conference | 1996 European Design Automation Conference with EURO-VHDL'96 and Exhibition |
|---|---|
| Country/Territory | Switzerland |
| City | Geneva |
| Period | 16 Sept 1996 → 20 Sept 1996 |
Abstract
This paper presents a system level HW/SW partitioning methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. Starting from modelling of the signal processing scheme and of the available processor resources, performance and expense measures are estimated for a finite set of processor modules. Based on these measurements, a numerical optimization can be carried out by using mixed integer linear programming as mathematical framework, leading to a heterogeneous system, which is optimal in terms of area expense and throughput rate.
ASJC Scopus subject areas
- Engineering(all)
- Control and Systems Engineering
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1996. 120-125 Paper presented at 1996 European Design Automation Conference with EURO-VHDL'96 and Exhibition, Geneva, Switzerland.
Research output: Contribution to conference › Paper › Research › peer review
}
TY - CONF
T1 - System level HW/SW partitioning and optimization tool
AU - Schwiegershausen, M.
AU - Kropp, H.
AU - Pirsch, P.
PY - 1996
Y1 - 1996
N2 - This paper presents a system level HW/SW partitioning methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. Starting from modelling of the signal processing scheme and of the available processor resources, performance and expense measures are estimated for a finite set of processor modules. Based on these measurements, a numerical optimization can be carried out by using mixed integer linear programming as mathematical framework, leading to a heterogeneous system, which is optimal in terms of area expense and throughput rate.
AB - This paper presents a system level HW/SW partitioning methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. Starting from modelling of the signal processing scheme and of the available processor resources, performance and expense measures are estimated for a finite set of processor modules. Based on these measurements, a numerical optimization can be carried out by using mixed integer linear programming as mathematical framework, leading to a heterogeneous system, which is optimal in terms of area expense and throughput rate.
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M3 - Paper
AN - SCOPUS:0029728618
SP - 120
EP - 125
T2 - 1996 European Design Automation Conference with EURO-VHDL'96 and Exhibition
Y2 - 16 September 1996 through 20 September 1996
ER -