Details
| Original language | English |
|---|---|
| Title of host publication | 2015 IEEE 27th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 341-344 |
| Number of pages | 4 |
| ISBN (electronic) | 9781479962594 |
| Publication status | Published - 12 Jun 2015 |
| Externally published | Yes |
| Event | 27th IEEE International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015 - Hong Kong, China Duration: 10 May 2015 → 14 May 2015 |
Publication series
| Name | Proceedings of the International Symposium on Power Semiconductor Devices and ICs |
|---|---|
| Volume | 2015-June |
| ISSN (Print) | 1063-6854 |
Abstract
Substrate coupling is a critical failure mechanism especially in fast-switching integrated power stages controlling high-side NMOS power FETs. The parasitic coupling across the substrate in integrated power stages at rise times of up to 500ps and input voltages of up to 40V is investigated in this paper. The coupling has been studied for the power stage of an integrated buck converter. In particular, dedicated diverting and isolation structures against substrate coupling are analyzed by simulations and evaluated with measurements from test chips in 180nm high-voltage BiCMOS. The results are compared regarding effectiveness, area as well as implementation effort and cost. Back-side metalization shows superior characteristics with nearly 100% noise suppression. Readily available p-guard ring structures bring 75% disturbance reduction. The results are applicable to advanced and future power management solutions with fully integrated switched-mode power supplies at switching frequencies >10 MHz.
ASJC Scopus subject areas
- Engineering(all)
- General Engineering
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2015 IEEE 27th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 341-344 7123459 (Proceedings of the International Symposium on Power Semiconductor Devices and ICs; Vol. 2015-June).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Substrate coupling in fast-switching integrated power stages
AU - Wittmann, Juergen
AU - Rindfleisch, Christoph
AU - Wicht, Bernhard
N1 - Publisher Copyright: © 2015 IEEE.
PY - 2015/6/12
Y1 - 2015/6/12
N2 - Substrate coupling is a critical failure mechanism especially in fast-switching integrated power stages controlling high-side NMOS power FETs. The parasitic coupling across the substrate in integrated power stages at rise times of up to 500ps and input voltages of up to 40V is investigated in this paper. The coupling has been studied for the power stage of an integrated buck converter. In particular, dedicated diverting and isolation structures against substrate coupling are analyzed by simulations and evaluated with measurements from test chips in 180nm high-voltage BiCMOS. The results are compared regarding effectiveness, area as well as implementation effort and cost. Back-side metalization shows superior characteristics with nearly 100% noise suppression. Readily available p-guard ring structures bring 75% disturbance reduction. The results are applicable to advanced and future power management solutions with fully integrated switched-mode power supplies at switching frequencies >10 MHz.
AB - Substrate coupling is a critical failure mechanism especially in fast-switching integrated power stages controlling high-side NMOS power FETs. The parasitic coupling across the substrate in integrated power stages at rise times of up to 500ps and input voltages of up to 40V is investigated in this paper. The coupling has been studied for the power stage of an integrated buck converter. In particular, dedicated diverting and isolation structures against substrate coupling are analyzed by simulations and evaluated with measurements from test chips in 180nm high-voltage BiCMOS. The results are compared regarding effectiveness, area as well as implementation effort and cost. Back-side metalization shows superior characteristics with nearly 100% noise suppression. Readily available p-guard ring structures bring 75% disturbance reduction. The results are applicable to advanced and future power management solutions with fully integrated switched-mode power supplies at switching frequencies >10 MHz.
UR - http://www.scopus.com/inward/record.url?scp=84944676616&partnerID=8YFLogxK
U2 - 10.1109/ISPSD.2015.7123459
DO - 10.1109/ISPSD.2015.7123459
M3 - Conference contribution
AN - SCOPUS:84944676616
T3 - Proceedings of the International Symposium on Power Semiconductor Devices and ICs
SP - 341
EP - 344
BT - 2015 IEEE 27th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 27th IEEE International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015
Y2 - 10 May 2015 through 14 May 2015
ER -