Details
| Original language | English |
|---|---|
| Pages | 77-84 |
| Number of pages | 8 |
| Publication status | Published - 2018 |
Abstract
The growing complexity of VLSI designs demands for continuous performance improvement of Electronic Design Automation (EDA) applications. Tradionally, part of this performance delta has been reached by leveraging the improvements in the single threaded performance of common processors. Unfortunately processor speeds have mostly plateaued in recent years. However, the advent of freely programmable GPUs allowed their use as highly parallel systems for a variety of computational use cases, making them an attractive device for reaching performance goals. In this paper, we introduce STP, a quadratic placement implementation, which leverages the computational power of GPUs as well as multicore CPUs in order to speed up execution.
Keywords
- Electronic Design Automation, Parallel Processing, Very Large Scale Integration
ASJC Scopus subject areas
- Computer Science(all)
- Computer Networks and Communications
- Computer Science(all)
- Hardware and Architecture
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2018. 77-84.
Research output: Contribution to conference › Paper › Research › peer review
}
TY - CONF
T1 - STP - A Quadratic VLSI Placement Tool Using Graphic Processing Units.
AU - Bredthauer, Bjorn
AU - Olbrich, Markus
AU - Barke, Erich
N1 - Funding information: Most of this research has been focused on the CUDA API, which is exclusive to NVIDIA GPUs, instead of the more broadly supported OpenCL API. This can partly be attributed to better support by NVIDIA, particularly their GPU Grant Program where NVIDIA gives a limited number of GPUs to academic institutions for research purposes. However, the result is that GPUs by AMD, the other big manufacturer, are severely underrepresented in academic research.
PY - 2018
Y1 - 2018
N2 - The growing complexity of VLSI designs demands for continuous performance improvement of Electronic Design Automation (EDA) applications. Tradionally, part of this performance delta has been reached by leveraging the improvements in the single threaded performance of common processors. Unfortunately processor speeds have mostly plateaued in recent years. However, the advent of freely programmable GPUs allowed their use as highly parallel systems for a variety of computational use cases, making them an attractive device for reaching performance goals. In this paper, we introduce STP, a quadratic placement implementation, which leverages the computational power of GPUs as well as multicore CPUs in order to speed up execution.
AB - The growing complexity of VLSI designs demands for continuous performance improvement of Electronic Design Automation (EDA) applications. Tradionally, part of this performance delta has been reached by leveraging the improvements in the single threaded performance of common processors. Unfortunately processor speeds have mostly plateaued in recent years. However, the advent of freely programmable GPUs allowed their use as highly parallel systems for a variety of computational use cases, making them an attractive device for reaching performance goals. In this paper, we introduce STP, a quadratic placement implementation, which leverages the computational power of GPUs as well as multicore CPUs in order to speed up execution.
KW - Electronic Design Automation
KW - Parallel Processing
KW - Very Large Scale Integration
UR - http://www.scopus.com/inward/record.url?scp=85053924253&partnerID=8YFLogxK
U2 - 10.1109/ispdc2018.2018.00020
DO - 10.1109/ispdc2018.2018.00020
M3 - Paper
SP - 77
EP - 84
ER -