Details
| Original language | English |
|---|---|
| Title of host publication | ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) |
| Pages | 265-268 |
| Number of pages | 4 |
| ISBN (electronic) | 978-1-6654-8494-7 |
| Publication status | Published - 2022 |
Abstract
Keywords
- 22nm FD-SOI, ABB, ASIC, ASIP, Tensilica, hearing aid, instruction extension, low power, system on chip (SoC)
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Electrical and Electronic Engineering
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Physics and Astronomy(all)
- Instrumentation
- Computer Science(all)
- Artificial Intelligence
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ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC). 2022. p. 265-268.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - SmartHeaP
T2 - A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI
AU - Karrenbauer, Jens Christian
AU - Klein, Simon Christian
AU - Schönewald, Sven Johannes
AU - Gerlach, Lukas Konrad
AU - Blawat, Meinolf
AU - Benndorf, Jens
AU - Blume, Holger Christoph
N1 - Funding Information: This work was funded by the Federal Ministry of Education and Research of Germany (BMBF) - project number 16ES0759. We also like to thank the partners for the excellent cooperation, especially Hörzentrum Oldenburg for the algorithmic support, Cadence Design Systems for providing the Tensilica and other IPs and support related EDA tools, SoC and architecture design methodology, and GlobalFoundries for the fabricated 22 FDX silicon.
PY - 2022
Y1 - 2022
N2 - To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm² . The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.
AB - To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm² . The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.
KW - 22nm FD-SOI
KW - ABB
KW - ASIC
KW - ASIP
KW - Tensilica
KW - hearing aid
KW - instruction extension
KW - low power
KW - system on chip (SoC)
UR - http://www.scopus.com/inward/record.url?scp=85141502799&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC55480.2022.9911325
DO - 10.1109/ESSCIRC55480.2022.9911325
M3 - Conference contribution
SN - 978-1-6654-8493-0
SN - 978-1-6654-8495-4
SP - 265
EP - 268
BT - ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
ER -