Details
| Original language | English |
|---|---|
| Pages (from-to) | 23-32 |
| Number of pages | 10 |
| Journal | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |
| Publication status | Published - 2000 |
| Event | 2000 IEEE Workshop on Signal Processing Systems (SIPS 2000) - Lafayette, LA, USA Duration: 11 Oct 2000 → 13 Oct 2000 |
Abstract
A programmable single-chip multiprocessor system for video signal processing applications has been developed. It integrates four processing nodes with on-chip DRAM and application-specific interfaces. The embedded DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing node. Methods for efficient usage of the integrated memory are discussed and the concept for a MPEG2 video encoder/decoder implementation is presented.
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In: IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 2000, p. 23-32.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - Single-chip video signal processing system with embedded DRAM
AU - Hilgenstock, Joerg
AU - Herrmann, Klaus
AU - Moch, Soeren
AU - Pirsch, Peter
PY - 2000
Y1 - 2000
N2 - A programmable single-chip multiprocessor system for video signal processing applications has been developed. It integrates four processing nodes with on-chip DRAM and application-specific interfaces. The embedded DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing node. Methods for efficient usage of the integrated memory are discussed and the concept for a MPEG2 video encoder/decoder implementation is presented.
AB - A programmable single-chip multiprocessor system for video signal processing applications has been developed. It integrates four processing nodes with on-chip DRAM and application-specific interfaces. The embedded DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing node. Methods for efficient usage of the integrated memory are discussed and the concept for a MPEG2 video encoder/decoder implementation is presented.
UR - http://www.scopus.com/inward/record.url?scp=0034500770&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0034500770
SP - 23
EP - 32
JO - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
JF - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SN - 1520-6130
T2 - 2000 IEEE Workshop on Signal Processing Systems (SIPS 2000)
Y2 - 11 October 2000 through 13 October 2000
ER -