Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings of SPIE |
| Subtitle of host publication | The International Society for Optical Engineering |
| Pages | 1753-1764 |
| Number of pages | 12 |
| Edition | p 3 |
| Publication status | Published - 1994 |
| Event | Visual Communications and Image Processing '94 - Chicago, IL, USA Duration: 25 Sept 1994 → 29 Sept 1994 |
Publication series
| Name | Proceedings of SPIE - The International Society for Optical Engineering |
|---|---|
| Number | p 3 |
| Volume | 2308 |
| ISSN (Print) | 0277-786X |
Abstract
For real-time implementation of image processing applications a general purpose Single Instruction/Multiple Data multiprocessor is proposed. The processor consists of an array of data paths, embedded in a two stage memory hierarchy, built of a shared memory with conflict free parallel access in shape of a matrix and a local cache, autonomously addressable by the data paths. The array is controlled by a Reduced Instruction Set Controller with load/store architecture and a fixed field coded very long instruction word. A six stage instruction pipeline leads to a low cycle time of the processor. To provide the necessary flexibility of the array processor even for the parallel processing of complex algorithms, a three stage autonomous controlling hierarchy for the processing units has been implemented. This concept leads to a high level language programmable homogeneous architecture with sustained performance on a wide spectrum of image processing algorithms. For an array of 16 processing units at 100 MHz clock frequency, an arithmetic processing power of 2.0 - 2.4 gigaoperations per second for several algorithms is achieved.
ASJC Scopus subject areas
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Physics and Astronomy(all)
- Condensed Matter Physics
- Computer Science(all)
- Computer Science Applications
- Mathematics(all)
- Applied Mathematics
- Engineering(all)
- Electrical and Electronic Engineering
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Proceedings of SPIE : The International Society for Optical Engineering. p 3. ed. 1994. p. 1753-1764 (Proceedings of SPIE - The International Society for Optical Engineering; Vol. 2308, No. p 3).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Single-chip highly parallel architecture for image processing applications
AU - Kneip, Johannes
AU - Roenner, Karsten
AU - Pirsch, Peter
PY - 1994
Y1 - 1994
N2 - For real-time implementation of image processing applications a general purpose Single Instruction/Multiple Data multiprocessor is proposed. The processor consists of an array of data paths, embedded in a two stage memory hierarchy, built of a shared memory with conflict free parallel access in shape of a matrix and a local cache, autonomously addressable by the data paths. The array is controlled by a Reduced Instruction Set Controller with load/store architecture and a fixed field coded very long instruction word. A six stage instruction pipeline leads to a low cycle time of the processor. To provide the necessary flexibility of the array processor even for the parallel processing of complex algorithms, a three stage autonomous controlling hierarchy for the processing units has been implemented. This concept leads to a high level language programmable homogeneous architecture with sustained performance on a wide spectrum of image processing algorithms. For an array of 16 processing units at 100 MHz clock frequency, an arithmetic processing power of 2.0 - 2.4 gigaoperations per second for several algorithms is achieved.
AB - For real-time implementation of image processing applications a general purpose Single Instruction/Multiple Data multiprocessor is proposed. The processor consists of an array of data paths, embedded in a two stage memory hierarchy, built of a shared memory with conflict free parallel access in shape of a matrix and a local cache, autonomously addressable by the data paths. The array is controlled by a Reduced Instruction Set Controller with load/store architecture and a fixed field coded very long instruction word. A six stage instruction pipeline leads to a low cycle time of the processor. To provide the necessary flexibility of the array processor even for the parallel processing of complex algorithms, a three stage autonomous controlling hierarchy for the processing units has been implemented. This concept leads to a high level language programmable homogeneous architecture with sustained performance on a wide spectrum of image processing algorithms. For an array of 16 processing units at 100 MHz clock frequency, an arithmetic processing power of 2.0 - 2.4 gigaoperations per second for several algorithms is achieved.
UR - http://www.scopus.com/inward/record.url?scp=0028735726&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0028735726
SN - 081941638X
T3 - Proceedings of SPIE - The International Society for Optical Engineering
SP - 1753
EP - 1764
BT - Proceedings of SPIE
T2 - Visual Communications and Image Processing '94
Y2 - 25 September 1994 through 29 September 1994
ER -