Details
| Original language | English |
|---|---|
| Title of host publication | 2017 18th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (electronic) | 9781509043446 |
| Publication status | Published - 10 May 2017 |
| Event | 18th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2017 - Dresden, Germany Duration: 3 Apr 2017 → 5 Apr 2017 |
Abstract
The metal layout design influences the reliability of the metallization in semiconductor products. An optimized design of the interconnect stack can help to reduce the incidence of dielectric and passivation cracking during Joule heating of the metallization in semiconductor back end of line (BEOL) structures. The elements of the metal stack have different material properties. Thermal stress from Joule heating can cause mismatch in thermal expansion between the materials. This can lead to high stress gradients. The paper shows the comparison of the standard design versus the Highly Robust (HiRo) metallization layout. The evaluation is done for an AlCu metallization with W-plugs in a 180 nm technology node with a metal stack with thick metal (∼3 μm thick) on top. The simulation results show better protection against thermal stress caused by Joule heating for the HiRo-layout.
ASJC Scopus subject areas
- Engineering(all)
- Mechanical Engineering
- Engineering(all)
- Mechanics of Materials
- Engineering(all)
- Electrical and Electronic Engineering
- Mathematics(all)
- Modelling and Simulation
- Mathematics(all)
- Numerical Analysis
- Engineering(all)
- Safety, Risk, Reliability and Quality
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2017 18th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 7926226.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Simulation investigations for the comparison of standard and highly robust AlCu thick metal tracks
AU - Sethu, Raj Sekar
AU - Hein, Verena
AU - Erstling, Marco
AU - Weide-Zaage, Kirsten
N1 - Publisher Copyright: © 2017 IEEE. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2017/5/10
Y1 - 2017/5/10
N2 - The metal layout design influences the reliability of the metallization in semiconductor products. An optimized design of the interconnect stack can help to reduce the incidence of dielectric and passivation cracking during Joule heating of the metallization in semiconductor back end of line (BEOL) structures. The elements of the metal stack have different material properties. Thermal stress from Joule heating can cause mismatch in thermal expansion between the materials. This can lead to high stress gradients. The paper shows the comparison of the standard design versus the Highly Robust (HiRo) metallization layout. The evaluation is done for an AlCu metallization with W-plugs in a 180 nm technology node with a metal stack with thick metal (∼3 μm thick) on top. The simulation results show better protection against thermal stress caused by Joule heating for the HiRo-layout.
AB - The metal layout design influences the reliability of the metallization in semiconductor products. An optimized design of the interconnect stack can help to reduce the incidence of dielectric and passivation cracking during Joule heating of the metallization in semiconductor back end of line (BEOL) structures. The elements of the metal stack have different material properties. Thermal stress from Joule heating can cause mismatch in thermal expansion between the materials. This can lead to high stress gradients. The paper shows the comparison of the standard design versus the Highly Robust (HiRo) metallization layout. The evaluation is done for an AlCu metallization with W-plugs in a 180 nm technology node with a metal stack with thick metal (∼3 μm thick) on top. The simulation results show better protection against thermal stress caused by Joule heating for the HiRo-layout.
UR - http://www.scopus.com/inward/record.url?scp=85020230707&partnerID=8YFLogxK
U2 - 10.1109/eurosime.2017.7926226
DO - 10.1109/eurosime.2017.7926226
M3 - Conference contribution
AN - SCOPUS:85020230707
BT - 2017 18th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 18th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2017
Y2 - 3 April 2017 through 5 April 2017
ER -