Details
| Original language | English |
|---|---|
| Title of host publication | Proc Int Conf Wafer Scale Integr |
| Editors | Earl Swartzlander, Joe Brewer |
| Pages | 345-354 |
| Number of pages | 10 |
| Publication status | Published - 1989 |
| Event | International Conference on Wafer Scale Integration - San Francisco, United States Duration: 3 Jan 1989 → 5 Jan 1989 |
Publication series
| Name | Proc Int Conf Wafer Scale Integr |
|---|
Abstract
Different fault mechanisms in interconnect systems are considered, and their fault behavior is discussed. To diagnose these faults by a digital test, special features of test pattern choice and design modifications are proposed. In contrast with existing tests for VLSI circuits, the specific dynamic behavior of large line systems in wafer-scale integration (WSI) must be taken into account. Analog simulations for opens, shorts, and delay faults were necessary. A special simulator called LISIM was used, since existing tools have proved to be of little value for simulating lossy line systems. From these results a fault diagnosis by a digital test turns out to be problematic, since a safe diagnosis of the considered faults is not gauranteed. In some cases this problem can be avoided by applying special test patterns. Additionally, design modifications are proposed, so that all these types of faults can be detected. The modifications do not affect the signal-to-noise ratio more than usual designs, and do not lend to an additional delay.
ASJC Scopus subject areas
- Engineering(all)
- General Engineering
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Proc Int Conf Wafer Scale Integr. ed. / Earl Swartzlander; Joe Brewer. 1989. p. 345-354 (Proc Int Conf Wafer Scale Integr).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Simulation and test of faults in WSI interconnect systems.
AU - Gruetzner, M.
AU - Grabinski, H.
PY - 1989
Y1 - 1989
N2 - Different fault mechanisms in interconnect systems are considered, and their fault behavior is discussed. To diagnose these faults by a digital test, special features of test pattern choice and design modifications are proposed. In contrast with existing tests for VLSI circuits, the specific dynamic behavior of large line systems in wafer-scale integration (WSI) must be taken into account. Analog simulations for opens, shorts, and delay faults were necessary. A special simulator called LISIM was used, since existing tools have proved to be of little value for simulating lossy line systems. From these results a fault diagnosis by a digital test turns out to be problematic, since a safe diagnosis of the considered faults is not gauranteed. In some cases this problem can be avoided by applying special test patterns. Additionally, design modifications are proposed, so that all these types of faults can be detected. The modifications do not affect the signal-to-noise ratio more than usual designs, and do not lend to an additional delay.
AB - Different fault mechanisms in interconnect systems are considered, and their fault behavior is discussed. To diagnose these faults by a digital test, special features of test pattern choice and design modifications are proposed. In contrast with existing tests for VLSI circuits, the specific dynamic behavior of large line systems in wafer-scale integration (WSI) must be taken into account. Analog simulations for opens, shorts, and delay faults were necessary. A special simulator called LISIM was used, since existing tools have proved to be of little value for simulating lossy line systems. From these results a fault diagnosis by a digital test turns out to be problematic, since a safe diagnosis of the considered faults is not gauranteed. In some cases this problem can be avoided by applying special test patterns. Additionally, design modifications are proposed, so that all these types of faults can be detected. The modifications do not affect the signal-to-noise ratio more than usual designs, and do not lend to an additional delay.
UR - http://www.scopus.com/inward/record.url?scp=0024864076&partnerID=8YFLogxK
U2 - 10.1109/WAFER.1989.47565
DO - 10.1109/WAFER.1989.47565
M3 - Conference contribution
AN - SCOPUS:0024864076
SN - 0818699019
T3 - Proc Int Conf Wafer Scale Integr
SP - 345
EP - 354
BT - Proc Int Conf Wafer Scale Integr
A2 - Swartzlander, Earl
A2 - Brewer, Joe
T2 - International Conference on Wafer Scale Integration
Y2 - 3 January 1989 through 5 January 1989
ER -