Signal integrity problems in deep submicron arising from interconnects between cores

Research output: Contribution to conference › Paper › Research › peer review

Authors

  • P. Nordholz
  • D. Treytnar
  • J. Otterstedt
  • H. Grabinski
  • D. Niggemeyer
  • T. W. Williams

Research Organisations

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Details

Original languageEnglish
Pages28-33
Number of pages6
Publication statusPublished - 1998
Event1998 16th IEEE VLSI Test Symposium - Monterey, United States
Duration: 26 Apr 1998 → 30 Apr 1998

Conference

Conference1998 16th IEEE VLSI Test Symposium
Country/TerritoryUnited States
CityMonterey
Period26 Apr 1998 → 30 Apr 1998

Abstract

The SIA Roadmap shows a very aggressive drive to deep submicron designs. A significant corner stone in the industries' ability to utilize this tremendous capabilities is the usage of reusable cores. When employing cores, one must be sensitive to the quality of the interconnects which will carry signals between cores and the ASIC portion of the network. In this work we will use an extremely accurate line simulator which solves the transmission line equations derived from Maxwell's equations for the simulation of line systems. We will show that the coupling between bus lines is significant, since the signal delay can be increased and even hazards can occur. Furthermore, these effects depend on the set of input signals of all bus lines and the skew between the individual input signals. The lines' cross sections are taken from the SIA Roadmap going from 0.35 μm technology design down to 0.10 μm technology design.

ASJC Scopus subject areas

Cite this

Signal integrity problems in deep submicron arising from interconnects between cores. / Nordholz, P.; Treytnar, D.; Otterstedt, J. et al.
1998. 28-33 Paper presented at 1998 16th IEEE VLSI Test Symposium, Monterey, California, United States.

Research output: Contribution to conference › Paper › Research › peer review

Nordholz, P, Treytnar, D, Otterstedt, J, Grabinski, H, Niggemeyer, D & Williams, TW 1998, 'Signal integrity problems in deep submicron arising from interconnects between cores', Paper presented at 1998 16th IEEE VLSI Test Symposium, Monterey, United States, 26 Apr 1998 - 30 Apr 1998 pp. 28-33. https://doi.org/10.1109/VTEST.1998.670845
Nordholz, P., Treytnar, D., Otterstedt, J., Grabinski, H., Niggemeyer, D., & Williams, T. W. (1998). Signal integrity problems in deep submicron arising from interconnects between cores. 28-33. Paper presented at 1998 16th IEEE VLSI Test Symposium, Monterey, California, United States. https://doi.org/10.1109/VTEST.1998.670845
Nordholz P, Treytnar D, Otterstedt J, Grabinski H, Niggemeyer D, Williams TW. Signal integrity problems in deep submicron arising from interconnects between cores. 1998. Paper presented at 1998 16th IEEE VLSI Test Symposium, Monterey, California, United States. doi: 10.1109/VTEST.1998.670845
Nordholz, P. ; Treytnar, D. ; Otterstedt, J. et al. / Signal integrity problems in deep submicron arising from interconnects between cores. Paper presented at 1998 16th IEEE VLSI Test Symposium, Monterey, California, United States.6 p.
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@conference{724c673d31e741c9900b06e9d51bf6a0,
title = "Signal integrity problems in deep submicron arising from interconnects between cores",
abstract = "The SIA Roadmap shows a very aggressive drive to deep submicron designs. A significant corner stone in the industries' ability to utilize this tremendous capabilities is the usage of reusable cores. When employing cores, one must be sensitive to the quality of the interconnects which will carry signals between cores and the ASIC portion of the network. In this work we will use an extremely accurate line simulator which solves the transmission line equations derived from Maxwell's equations for the simulation of line systems. We will show that the coupling between bus lines is significant, since the signal delay can be increased and even hazards can occur. Furthermore, these effects depend on the set of input signals of all bus lines and the skew between the individual input signals. The lines' cross sections are taken from the SIA Roadmap going from 0.35 μm technology design down to 0.10 μm technology design.",
author = "P. Nordholz and D. Treytnar and J. Otterstedt and H. Grabinski and D. Niggemeyer and Williams, {T. W.}",
year = "1998",
doi = "10.1109/VTEST.1998.670845",
language = "English",
pages = "28--33",
note = "1998 16th IEEE VLSI Test Symposium ; Conference date: 26-04-1998 Through 30-04-1998",

}

Download

TY - CONF

T1 - Signal integrity problems in deep submicron arising from interconnects between cores

AU - Nordholz, P.

AU - Treytnar, D.

AU - Otterstedt, J.

AU - Grabinski, H.

AU - Niggemeyer, D.

AU - Williams, T. W.

PY - 1998

Y1 - 1998

N2 - The SIA Roadmap shows a very aggressive drive to deep submicron designs. A significant corner stone in the industries' ability to utilize this tremendous capabilities is the usage of reusable cores. When employing cores, one must be sensitive to the quality of the interconnects which will carry signals between cores and the ASIC portion of the network. In this work we will use an extremely accurate line simulator which solves the transmission line equations derived from Maxwell's equations for the simulation of line systems. We will show that the coupling between bus lines is significant, since the signal delay can be increased and even hazards can occur. Furthermore, these effects depend on the set of input signals of all bus lines and the skew between the individual input signals. The lines' cross sections are taken from the SIA Roadmap going from 0.35 μm technology design down to 0.10 μm technology design.

AB - The SIA Roadmap shows a very aggressive drive to deep submicron designs. A significant corner stone in the industries' ability to utilize this tremendous capabilities is the usage of reusable cores. When employing cores, one must be sensitive to the quality of the interconnects which will carry signals between cores and the ASIC portion of the network. In this work we will use an extremely accurate line simulator which solves the transmission line equations derived from Maxwell's equations for the simulation of line systems. We will show that the coupling between bus lines is significant, since the signal delay can be increased and even hazards can occur. Furthermore, these effects depend on the set of input signals of all bus lines and the skew between the individual input signals. The lines' cross sections are taken from the SIA Roadmap going from 0.35 μm technology design down to 0.10 μm technology design.

UR - http://www.scopus.com/inward/record.url?scp=0032321261&partnerID=8YFLogxK

U2 - 10.1109/VTEST.1998.670845

DO - 10.1109/VTEST.1998.670845

M3 - Paper

AN - SCOPUS:0032321261

SP - 28

EP - 33

T2 - 1998 16th IEEE VLSI Test Symposium

Y2 - 26 April 1998 through 30 April 1998

ER -