SAFER SLOTH: Efficient, Hardware-Tailored Memory Protection

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Authors

  • Daniel Danner
  • Rainer Müller
  • Wolfgang Schröder-Preikschat
  • Wanja Hofer
  • Daniel Lohmann

External Research Organisations

  • Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU Erlangen-Nürnberg)
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Details

Original languageEnglish
Title of host publication2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)
Pages37-47
Number of pages11
ISBN (electronic)978-1-4799-4829-1
Publication statusPublished - 19 Jan 2015
Externally publishedYes
Event2014 20th IEEE Real Time and Embedded Technology and Applications Symposium, RTAS 2014 - Berlin, Germany
Duration: 15 Apr 201417 Apr 2014

Publication series

NameReal-Time Technology and Applications - Proceedings
ISSN (Print)1080-1812

Abstract

The goal of the SLOTH family of operating system kernels is to provide a unified priority space to the real-time applications. By automated mapping of tasks to interrupts, we eliminate rate-monotonic priority inversion and increase execution determinism. In its standard implementation, however, SLOTH has been criticized for being unsafe, since interrupt service routines are executed in supervisor mode. SAFER SLOTH mitigates this shortcoming - while keeping the favorable properties of SLOTH - and provides a safe and isolated execution environment for application tasks. Adopting the SLOTH philosophy of embracing and exploiting hardware particularities, its generative approach automatically tailors the system to both the application and the target architecture. We achieve efficient MPU-based memory protection at reduced latency and low performance overhead by leveraging code inlining and compiler optimizations. In comparison to a commercial AUTOSAR OS, SAFER SLOTH achieves speedups between 8x (worst case) and 23x (best case) on kernel latencies while retaining the SLOTH advantages of strict priority obedience, excellent determinism and small memory footprints.

ASJC Scopus subject areas

Cite this

SAFER SLOTH: Efficient, Hardware-Tailored Memory Protection. / Danner, Daniel; Müller, Rainer; Schröder-Preikschat, Wolfgang et al.
2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). 2015. p. 37-47 (Real-Time Technology and Applications - Proceedings).

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Danner, D, Müller, R, Schröder-Preikschat, W, Hofer, W & Lohmann, D 2015, SAFER SLOTH: Efficient, Hardware-Tailored Memory Protection. in 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). Real-Time Technology and Applications - Proceedings, pp. 37-47, 2014 20th IEEE Real Time and Embedded Technology and Applications Symposium, RTAS 2014, Berlin, Germany, 15 Apr 2014. https://doi.org/10.1109/RTAS.2014.6925989
Danner, D., Müller, R., Schröder-Preikschat, W., Hofer, W., & Lohmann, D. (2015). SAFER SLOTH: Efficient, Hardware-Tailored Memory Protection. In 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS) (pp. 37-47). (Real-Time Technology and Applications - Proceedings). https://doi.org/10.1109/RTAS.2014.6925989
Danner D, Müller R, Schröder-Preikschat W, Hofer W, Lohmann D. SAFER SLOTH: Efficient, Hardware-Tailored Memory Protection. In 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). 2015. p. 37-47. (Real-Time Technology and Applications - Proceedings). doi: 10.1109/RTAS.2014.6925989
Danner, Daniel ; Müller, Rainer ; Schröder-Preikschat, Wolfgang et al. / SAFER SLOTH: Efficient, Hardware-Tailored Memory Protection. 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). 2015. pp. 37-47 (Real-Time Technology and Applications - Proceedings).
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