Details
| Original language | English |
|---|---|
| Pages (from-to) | 1988-1994 |
| Number of pages | 7 |
| Journal | Microelectronics reliability |
| Volume | 54 |
| Issue number | 9-10 |
| Publication status | Published - 1 Sept 2014 |
Abstract
This paper describes applied reliability for semiconductor components in Wafer Level Chip Scale Packages (CSP). To develop and qualify reliable products, the failure mechanism driven approach is to be followed instead of the stress test driven one. This will be explained by elaborating on two failure mode cases assessed in WL-CSP: cracks in the passivation layer and top metal of the die/silicon and electromigration in the solder joints. A new TMCL test method is described that covers the direct (thermo) mechanical interaction between PCB and the die/design via the solder joint. In addition, the relevance of Finite Element Modeling to understand the origin of failure modes is shown which allows for optimizing designs and materials. Finally, the concept of life time prediction, starting from application use descriptions and mission profiles, is introduced. Reliability testing, modeling and life time prediction/reliability statistics are combined in one framework to accommodate for the creation of application specific, highly reliable components.
Keywords
- Electromigration, Finite Element Modeling, Life time prediction, Mission profile, Passivation cracks, Wafer Level Chip Scale Package
ASJC Scopus subject areas
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Physics and Astronomy(all)
- Atomic and Molecular Physics, and Optics
- Engineering(all)
- Safety, Risk, Reliability and Quality
- Physics and Astronomy(all)
- Condensed Matter Physics
- Materials Science(all)
- Surfaces, Coatings and Films
- Engineering(all)
- Electrical and Electronic Engineering
Cite this
- Standard
- Harvard
- Apa
- Vancouver
- BibTeX
- RIS
In: Microelectronics reliability, Vol. 54, No. 9-10, 01.09.2014, p. 1988-1994.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Reliability of wafer level chip scale packages
AU - Rongen, R.
AU - Roucou, R.
AU - Vd Wel, P. J.
AU - Voogt, F.
AU - Swartjes, F.
AU - Weide-Zaage, K.
N1 - Publisher Copyright: © 2014 Elsevier Ltd. All rights reserved. Copyright: Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2014/9/1
Y1 - 2014/9/1
N2 - This paper describes applied reliability for semiconductor components in Wafer Level Chip Scale Packages (CSP). To develop and qualify reliable products, the failure mechanism driven approach is to be followed instead of the stress test driven one. This will be explained by elaborating on two failure mode cases assessed in WL-CSP: cracks in the passivation layer and top metal of the die/silicon and electromigration in the solder joints. A new TMCL test method is described that covers the direct (thermo) mechanical interaction between PCB and the die/design via the solder joint. In addition, the relevance of Finite Element Modeling to understand the origin of failure modes is shown which allows for optimizing designs and materials. Finally, the concept of life time prediction, starting from application use descriptions and mission profiles, is introduced. Reliability testing, modeling and life time prediction/reliability statistics are combined in one framework to accommodate for the creation of application specific, highly reliable components.
AB - This paper describes applied reliability for semiconductor components in Wafer Level Chip Scale Packages (CSP). To develop and qualify reliable products, the failure mechanism driven approach is to be followed instead of the stress test driven one. This will be explained by elaborating on two failure mode cases assessed in WL-CSP: cracks in the passivation layer and top metal of the die/silicon and electromigration in the solder joints. A new TMCL test method is described that covers the direct (thermo) mechanical interaction between PCB and the die/design via the solder joint. In addition, the relevance of Finite Element Modeling to understand the origin of failure modes is shown which allows for optimizing designs and materials. Finally, the concept of life time prediction, starting from application use descriptions and mission profiles, is introduced. Reliability testing, modeling and life time prediction/reliability statistics are combined in one framework to accommodate for the creation of application specific, highly reliable components.
KW - Electromigration
KW - Finite Element Modeling
KW - Life time prediction
KW - Mission profile
KW - Passivation cracks
KW - Wafer Level Chip Scale Package
UR - http://www.scopus.com/inward/record.url?scp=84908513560&partnerID=8YFLogxK
U2 - 10.1016/j.microrel.2014.07.012
DO - 10.1016/j.microrel.2014.07.012
M3 - Article
AN - SCOPUS:84908513560
VL - 54
SP - 1988
EP - 1994
JO - Microelectronics reliability
JF - Microelectronics reliability
SN - 0026-2714
IS - 9-10
ER -