Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings 1998 |
| Subtitle of host publication | Design and Automation Conference, DAC 1998 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 56-61 |
| Number of pages | 6 |
| ISBN (print) | 078034409X |
| Publication status | Published - 1 May 1998 |
| Event | 35th Design and Automation Conference, DAC 1998 - San Francisco, United States Duration: 15 Jun 1998 → 19 Jun 1998 |
Publication series
| Name | Proceedings - Design Automation Conference |
|---|---|
| ISSN (Print) | 0738-100X |
Abstract
Architecture and design of the HiPAR-DSP, a SIMD controlled signal processor with parallel data paths, VLIW and novel memory design is presented. The processor architecture is derived from an analysis of the target algorithms and specified in VHDL on register transfer level. A team of more than 20 graduate students covered the whole design process, including the synthesizable VHDL description, synthesis, routing and backannotation as the development of a complete software development environment. The 175 mm2, 0.5 μm 3LM CMOS design with 1.2 million transistors operates at 80 MHz and achieves a sustained performance of more than 600 million arithmetic operations.
ASJC Scopus subject areas
- Computer Science(all)
- Computer Science Applications
- Engineering(all)
- Control and Systems Engineering
- Engineering(all)
- Electrical and Electronic Engineering
- Mathematics(all)
- Modelling and Simulation
- Computer Science(all)
- Hardware and Architecture
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Proceedings 1998 : Design and Automation Conference, DAC 1998. Institute of Electrical and Electronics Engineers Inc., 1998. p. 56-61 724439 (Proceedings - Design Automation Conference).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Realization of a programmable parallel DSP for high performance image processing applications
AU - Wittenburg, Jens Peter
AU - Hinrichs, Willm
AU - Kneip, Johannes
AU - Ohmacht, Martin
AU - Bereković, Mladen
AU - Lieske, Hanno
AU - Kloos, Helge
AU - Pirsch, Peter
PY - 1998/5/1
Y1 - 1998/5/1
N2 - Architecture and design of the HiPAR-DSP, a SIMD controlled signal processor with parallel data paths, VLIW and novel memory design is presented. The processor architecture is derived from an analysis of the target algorithms and specified in VHDL on register transfer level. A team of more than 20 graduate students covered the whole design process, including the synthesizable VHDL description, synthesis, routing and backannotation as the development of a complete software development environment. The 175 mm2, 0.5 μm 3LM CMOS design with 1.2 million transistors operates at 80 MHz and achieves a sustained performance of more than 600 million arithmetic operations.
AB - Architecture and design of the HiPAR-DSP, a SIMD controlled signal processor with parallel data paths, VLIW and novel memory design is presented. The processor architecture is derived from an analysis of the target algorithms and specified in VHDL on register transfer level. A team of more than 20 graduate students covered the whole design process, including the synthesizable VHDL description, synthesis, routing and backannotation as the development of a complete software development environment. The 175 mm2, 0.5 μm 3LM CMOS design with 1.2 million transistors operates at 80 MHz and achieves a sustained performance of more than 600 million arithmetic operations.
UR - http://www.scopus.com/inward/record.url?scp=0031642082&partnerID=8YFLogxK
U2 - 10.1145/277044.277055
DO - 10.1145/277044.277055
M3 - Conference contribution
AN - SCOPUS:0031642082
SN - 078034409X
T3 - Proceedings - Design Automation Conference
SP - 56
EP - 61
BT - Proceedings 1998
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Design and Automation Conference, DAC 1998
Y2 - 15 June 1998 through 19 June 1998
ER -