Details
| Original language | English |
|---|---|
| Pages (from-to) | 32-40 |
| Number of pages | 9 |
| Journal | Lecture Notes in Computer Science |
| Volume | 3553 |
| Publication status | Published - 2005 |
| Event | 5th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2005 - Samos, Greece Duration: 18 Jul 2005 → 20 Jul 2005 |
Abstract
This paper describes a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The new methodology combines a typical ASIC flow with an FPGA flow focused on rapid prototyping. In order to make an exhaustive verification of the system architecture, a reference model that specifies the hardware implementation is used for validating both, HDL description and emulated system. Functional coverage in addition to traditional code coverage is used to test 100% of data, control and structural hazards of the system architecture. The reference model is also part of a stand-alone simulation environment. This allows hardware and application development be supported by a unique system model.
ASJC Scopus subject areas
- Mathematics(all)
- Theoretical Computer Science
- Computer Science(all)
- General Computer Science
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In: Lecture Notes in Computer Science, Vol. 3553, 2005, p. 32-40.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - RAPANUI
T2 - 5th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2005
AU - Payá Vayá, Guillermo
AU - Langerwerf, Javier Martín
AU - Pirsch, Peter
PY - 2005
Y1 - 2005
N2 - This paper describes a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The new methodology combines a typical ASIC flow with an FPGA flow focused on rapid prototyping. In order to make an exhaustive verification of the system architecture, a reference model that specifies the hardware implementation is used for validating both, HDL description and emulated system. Functional coverage in addition to traditional code coverage is used to test 100% of data, control and structural hazards of the system architecture. The reference model is also part of a stand-alone simulation environment. This allows hardware and application development be supported by a unique system model.
AB - This paper describes a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The new methodology combines a typical ASIC flow with an FPGA flow focused on rapid prototyping. In order to make an exhaustive verification of the system architecture, a reference model that specifies the hardware implementation is used for validating both, HDL description and emulated system. Functional coverage in addition to traditional code coverage is used to test 100% of data, control and structural hazards of the system architecture. The reference model is also part of a stand-alone simulation environment. This allows hardware and application development be supported by a unique system model.
UR - http://www.scopus.com/inward/record.url?scp=26444459761&partnerID=8YFLogxK
U2 - 10.1007/11512622_5
DO - 10.1007/11512622_5
M3 - Conference article
AN - SCOPUS:26444459761
VL - 3553
SP - 32
EP - 40
JO - Lecture Notes in Computer Science
JF - Lecture Notes in Computer Science
SN - 0302-9743
Y2 - 18 July 2005 through 20 July 2005
ER -