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RAPANUI: A case study in rapid prototyping for multiprocessor system-on-chip

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Authors

  • Guillermo Payá-Vayá
  • Javier Martín-Langerwerf
  • Peter Pirsch

Research Organisations

Details

Original languageEnglish
Title of host publicationProceedings
Subtitle of host publication10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007
Pages215-221
Number of pages7
Publication statusPublished - 2007
Event10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007 - Lubeck, Germany
Duration: 29 Aug 200731 Aug 2007

Publication series

NameProceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007

Abstract

This paper describes a case study in a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The goal of the presented methodology is to speed up and improve the verification flow of a multiprocessor system that will finally be implemented as an ASIC. The case study consists of a 64-bit compatible AMBA AHB system bus which connects up to 14 32-Bit RISC processors to a host interface. A typical parallel computing application has been implemented for the parameterized multiprocessor system. The employed FPGA emulation environment increases by up to 200 the simulation frequency of the global system on a workstation (2.2 GHz AMD Dual Opteron with 8 GB RAM). Moreover a stand-alone emulation can be performed at the maximum achievable frequency (65 MHz).

Keywords

    Case study, Design verification and modeling, Emulation, Prototyping

ASJC Scopus subject areas

Cite this

RAPANUI: A case study in rapid prototyping for multiprocessor system-on-chip. / Payá-Vayá, Guillermo; Martín-Langerwerf, Javier; Pirsch, Peter.
Proceedings: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007. 2007. p. 215-221 4341471 (Proceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007).

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Payá-Vayá, G, Martín-Langerwerf, J & Pirsch, P 2007, RAPANUI: A case study in rapid prototyping for multiprocessor system-on-chip. in Proceedings: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007., 4341471, Proceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007, pp. 215-221, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007, Lubeck, Germany, 29 Aug 2007. https://doi.org/10.1109/DSD.2007.4341471
Payá-Vayá, G., Martín-Langerwerf, J., & Pirsch, P. (2007). RAPANUI: A case study in rapid prototyping for multiprocessor system-on-chip. In Proceedings: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007 (pp. 215-221). Article 4341471 (Proceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007). https://doi.org/10.1109/DSD.2007.4341471
Payá-Vayá G, Martín-Langerwerf J, Pirsch P. RAPANUI: A case study in rapid prototyping for multiprocessor system-on-chip. In Proceedings: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007. 2007. p. 215-221. 4341471. (Proceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007). doi: 10.1109/DSD.2007.4341471
Payá-Vayá, Guillermo ; Martín-Langerwerf, Javier ; Pirsch, Peter. / RAPANUI : A case study in rapid prototyping for multiprocessor system-on-chip. Proceedings: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007. 2007. pp. 215-221 (Proceedings - 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007).
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