Details
| Original language | English |
|---|---|
| Title of host publication | IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06) |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 125-131 |
| Number of pages | 7 |
| ISBN (print) | 0769526829 |
| Publication status | Published - 4 Dec 2006 |
| Externally published | Yes |
| Event | IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006 - Steamboat Springs, CO, United States Duration: 11 Sept 2006 → 13 Sept 2006 |
Abstract
Embedding FPGAs (eFPGAs) in modern SoCs provides a high amount of flexibility while high-throughput digital signal processing algorithms can be realised efficiently. An analysis of eFPGA architectures and corresponding structural elements is presented to determine the optimisation potential for eFPGAs tailored to an arithmetic oriented application domain. The applied design flow incorporating an automated layout generation approach and the utilised simulation environment is discussed. An eFPGA macro designed and realised for arithmetic oriented applications is quantitatively compared to an actual commercial FPGA in terms of area, power consumption and delay time. It can be shown that this optimised eFPGA macro outperforms a state of the art commercial device for a couple of arithmetic operators which are commonly applied in arithmetic datapaths.
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Computer Science(all)
- Computer Networks and Communications
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IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06). Institute of Electrical and Electronics Engineers Inc., 2006. p. 125-131.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Quantitative analysis of embedded FPGA-architectures for arithmetic
AU - Von Sydow, T.
AU - Neumann, B.
AU - Blume, H.
AU - Noll, T. G.
PY - 2006/12/4
Y1 - 2006/12/4
N2 - Embedding FPGAs (eFPGAs) in modern SoCs provides a high amount of flexibility while high-throughput digital signal processing algorithms can be realised efficiently. An analysis of eFPGA architectures and corresponding structural elements is presented to determine the optimisation potential for eFPGAs tailored to an arithmetic oriented application domain. The applied design flow incorporating an automated layout generation approach and the utilised simulation environment is discussed. An eFPGA macro designed and realised for arithmetic oriented applications is quantitatively compared to an actual commercial FPGA in terms of area, power consumption and delay time. It can be shown that this optimised eFPGA macro outperforms a state of the art commercial device for a couple of arithmetic operators which are commonly applied in arithmetic datapaths.
AB - Embedding FPGAs (eFPGAs) in modern SoCs provides a high amount of flexibility while high-throughput digital signal processing algorithms can be realised efficiently. An analysis of eFPGA architectures and corresponding structural elements is presented to determine the optimisation potential for eFPGAs tailored to an arithmetic oriented application domain. The applied design flow incorporating an automated layout generation approach and the utilised simulation environment is discussed. An eFPGA macro designed and realised for arithmetic oriented applications is quantitatively compared to an actual commercial FPGA in terms of area, power consumption and delay time. It can be shown that this optimised eFPGA macro outperforms a state of the art commercial device for a couple of arithmetic operators which are commonly applied in arithmetic datapaths.
UR - http://www.scopus.com/inward/record.url?scp=34547446609&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2006.56
DO - 10.1109/ASAP.2006.56
M3 - Conference contribution
AN - SCOPUS:34547446609
SN - 0769526829
SP - 125
EP - 131
BT - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
Y2 - 11 September 2006 through 13 September 2006
ER -