Details
| Original language | English |
|---|---|
| Title of host publication | 2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC) |
| Pages | 1-9 |
| Number of pages | 9 |
| ISBN (electronic) | 978-1-6654-0627-7 |
| Publication status | Published - 2022 |
| Event | 2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC) - Västerås, Sweden Duration: 17 May 2022 → 18 May 2022 |
Abstract
While processing external events, in the form of interrupt requests (IRQs), is a key concern of digital control systems, processing these events can be of different importance for a system's functionality. Therefore, it is necessary, especially for real-Time systems, to ensure that the handling of low-priority IRQs does not interfere with high-priority interrupt-service routines (ISRs) to prevent priority inversions. While prioritizing ISRs on single-core machines is a long-solved problem, priority-strict IRQ handling in multi-core systems is, as we will show, quite challenging with current interrupt controllers.With PSIC, we propose a hardware/software co-design that ensures the priority-strict execution of the top-m ISRs on an m-core machine at minimal interruption-induced overheads. We developed a drop-in replacement for an off-The-shelf interrupt controller that delivers IRQs in strict priority order while achieving low delivering delays at moderate hardware costs. Combined with a minimal IRQ software subsystem, which requires no inter-core synchronization, PSIC guarantees a priority-strict ISR execution on multiple cores.
ASJC Scopus subject areas
- Engineering(all)
- Safety, Risk, Reliability and Quality
- Computer Science(all)
- Hardware and Architecture
- Computer Science(all)
- Computer Networks and Communications
- Computer Science(all)
- Computer Science Applications
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2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC). 2022. p. 1-9.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - PSIC
T2 - 2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC)
AU - Bargholz, Malte
AU - Dietrich, Christian
AU - Lohmann, Daniel
N1 - Funding information: ACKNOWLEDGMENTS We would like to thank Matthias Wolf and Christian Bewermeyer for their work on initial drafts of this idea. Furthermore, we also thank our anonymous reviewers for their constructive feedback. This work was funded by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) -391305160 (LO 1719/4-1).
PY - 2022
Y1 - 2022
N2 - While processing external events, in the form of interrupt requests (IRQs), is a key concern of digital control systems, processing these events can be of different importance for a system's functionality. Therefore, it is necessary, especially for real-Time systems, to ensure that the handling of low-priority IRQs does not interfere with high-priority interrupt-service routines (ISRs) to prevent priority inversions. While prioritizing ISRs on single-core machines is a long-solved problem, priority-strict IRQ handling in multi-core systems is, as we will show, quite challenging with current interrupt controllers.With PSIC, we propose a hardware/software co-design that ensures the priority-strict execution of the top-m ISRs on an m-core machine at minimal interruption-induced overheads. We developed a drop-in replacement for an off-The-shelf interrupt controller that delivers IRQs in strict priority order while achieving low delivering delays at moderate hardware costs. Combined with a minimal IRQ software subsystem, which requires no inter-core synchronization, PSIC guarantees a priority-strict ISR execution on multiple cores.
AB - While processing external events, in the form of interrupt requests (IRQs), is a key concern of digital control systems, processing these events can be of different importance for a system's functionality. Therefore, it is necessary, especially for real-Time systems, to ensure that the handling of low-priority IRQs does not interfere with high-priority interrupt-service routines (ISRs) to prevent priority inversions. While prioritizing ISRs on single-core machines is a long-solved problem, priority-strict IRQ handling in multi-core systems is, as we will show, quite challenging with current interrupt controllers.With PSIC, we propose a hardware/software co-design that ensures the priority-strict execution of the top-m ISRs on an m-core machine at minimal interruption-induced overheads. We developed a drop-in replacement for an off-The-shelf interrupt controller that delivers IRQs in strict priority order while achieving low delivering delays at moderate hardware costs. Combined with a minimal IRQ software subsystem, which requires no inter-core synchronization, PSIC guarantees a priority-strict ISR execution on multiple cores.
UR - http://www.scopus.com/inward/record.url?scp=85135369989&partnerID=8YFLogxK
U2 - 10.1109/ISORC52572.2022.9812796
DO - 10.1109/ISORC52572.2022.9812796
M3 - Conference contribution
SN - 978-1-6654-0628-4
SP - 1
EP - 9
BT - 2022 IEEE 25th International Symposium On Real-Time Distributed Computing (ISORC)
Y2 - 17 May 2022 through 18 May 2022
ER -