Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon |
| Pages | 98-103 |
| Number of pages | 6 |
| Publication status | Published - 1996 |
| Event | 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon - Austin, TX, USA Duration: 9 Oct 1996 → 11 Oct 1996 |
Publication series
| Name | Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon |
|---|---|
| ISSN (Print) | 1063-2204 |
Abstract
The architecture and implementation of a programmable processing element dedicated as building block for a large area integrated multiprocessor system is presented. The processor element allows an efficient implementation of video coding standards. It consists of a RISC processor supplemented by a low level coprocessor for computation intensive convolution-like tasks. Several of the processing elements can be bus-connected to built a coarse-grained MIMD based large area integrated multiprocessor system. Each of the processor elements provides high performance for video coding tasks in order to keep the overall number of required processing elements for complex real-time video coding applications small. A key feature of the processing element to support large area integration is a unidirectional data supply which allows reconfiguration strategies for the interconnection network. Furthermore on-chip program and data memories have been implemented in order to relax the overall bandwidth requirements of the large area integrated multiprocessor system.
ASJC Scopus subject areas
- Physics and Astronomy(all)
- Condensed Matter Physics
- Engineering(all)
- Electrical and Electronic Engineering
- Computer Science(all)
- Hardware and Architecture
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Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. 1996. p. 98-103 (Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Programmable processing element dedicated as building block for a large area integrated multiprocessor system
AU - Herrmann, Klaus
AU - Hilgenstock, Joerg
AU - Gaedke, Klaus
AU - Jeschke, Hartwig
AU - Pirsch, Peter
PY - 1996
Y1 - 1996
N2 - The architecture and implementation of a programmable processing element dedicated as building block for a large area integrated multiprocessor system is presented. The processor element allows an efficient implementation of video coding standards. It consists of a RISC processor supplemented by a low level coprocessor for computation intensive convolution-like tasks. Several of the processing elements can be bus-connected to built a coarse-grained MIMD based large area integrated multiprocessor system. Each of the processor elements provides high performance for video coding tasks in order to keep the overall number of required processing elements for complex real-time video coding applications small. A key feature of the processing element to support large area integration is a unidirectional data supply which allows reconfiguration strategies for the interconnection network. Furthermore on-chip program and data memories have been implemented in order to relax the overall bandwidth requirements of the large area integrated multiprocessor system.
AB - The architecture and implementation of a programmable processing element dedicated as building block for a large area integrated multiprocessor system is presented. The processor element allows an efficient implementation of video coding standards. It consists of a RISC processor supplemented by a low level coprocessor for computation intensive convolution-like tasks. Several of the processing elements can be bus-connected to built a coarse-grained MIMD based large area integrated multiprocessor system. Each of the processor elements provides high performance for video coding tasks in order to keep the overall number of required processing elements for complex real-time video coding applications small. A key feature of the processing element to support large area integration is a unidirectional data supply which allows reconfiguration strategies for the interconnection network. Furthermore on-chip program and data memories have been implemented in order to relax the overall bandwidth requirements of the large area integrated multiprocessor system.
UR - http://www.scopus.com/inward/record.url?scp=0030408889&partnerID=8YFLogxK
U2 - 10.1109/ICISS.1996.552416
DO - 10.1109/ICISS.1996.552416
M3 - Conference contribution
AN - SCOPUS:0030408889
SN - 0780336399
T3 - Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
SP - 98
EP - 103
BT - Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
T2 - 1996 8th Annual IEEE International Conference on Innovative Systems in Silicon
Y2 - 9 October 1996 through 11 October 1996
ER -