Details
| Original language | English |
|---|---|
| Publication status | Published - 2018 |
| Event | Cadence User Conference 2018 - München, Germany Duration: 7 May 2018 → 9 May 2018 |
Conference
| Conference | Cadence User Conference 2018 |
|---|---|
| Abbreviated title | CDN LIVE |
| Country/Territory | Germany |
| City | München |
| Period | 7 May 2018 → 9 May 2018 |
Abstract
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2018. Paper presented at Cadence User Conference 2018, München, Germany.
Research output: Contribution to conference › Paper › Research › peer review
}
TY - CONF
T1 - Processor Architecture Tradeoffs for On-Site Electronics in Harsh Environment
AU - Nolting, Stephan
AU - Gesper, Sven
AU - Schmider, Achim
AU - Weißbrich, Moritz
AU - Stuckenberg, Tobias
AU - Payá Vayá, Guillermo
AU - Blume, Holger Christoph
PY - 2018
Y1 - 2018
N2 - Microcontroller units placed in harsh environments are manufactured using large semiconductor technology nodes in order to provide reliable operation even at high temperatures or increased radiation exposition. As a drawback, these large technology nodes provide rather high gate propagation delays drastically reducing the system performance. Additionally, when reducing area costs and power consumption, the actual processor architecture becomes a major design point. A processor architecture is defined by several parameters like data path width, type of instruction execution, or the actual underlying architectural design paradigm. This work presents a design space exploration of four different architecture paradigms implemented for a 0.35μm high temperature SOI CMOS technology.
AB - Microcontroller units placed in harsh environments are manufactured using large semiconductor technology nodes in order to provide reliable operation even at high temperatures or increased radiation exposition. As a drawback, these large technology nodes provide rather high gate propagation delays drastically reducing the system performance. Additionally, when reducing area costs and power consumption, the actual processor architecture becomes a major design point. A processor architecture is defined by several parameters like data path width, type of instruction execution, or the actual underlying architectural design paradigm. This work presents a design space exploration of four different architecture paradigms implemented for a 0.35μm high temperature SOI CMOS technology.
M3 - Paper
T2 - Cadence User Conference 2018
Y2 - 7 May 2018 through 9 May 2018
ER -