Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor

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Authors

  • Peter Pirsch
  • Johannes Kneip
  • Karsten Roenner
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Details

Original languageEnglish
Pages (from-to)562-565
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
Publication statusPublished - 1995
EventThe 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995. Part 3 (of 3) - Seattle, United States
Duration: 30 Apr 19953 May 1995

Abstract

For the design of a highly parallel programmable videosignal processor, the parallelization resources and characteristic properties of image processing algorithms have been analyzed. Basing on the resulting algorithmic requirements, an architecture for a reduced instruction set processor with parallel data paths, called HiPAR-DSP has been deduced. The processor consists of 4 or 16 parallel data paths with local data caches, coupled by a shared memory with matrix type data access. Control, memory and arithmetic architecture of the processor are properly balanced and adapted to the control flow and data access patterns of algorithms, resulting in a remarkable high sustained processing power for a broad spectrum of image processing algorithms.

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Cite this

Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor. / Pirsch, Peter; Kneip, Johannes; Roenner, Karsten.
In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 1, 1995, p. 562-565.

Research output: Contribution to journalConference articleResearchpeer review

Pirsch, P, Kneip, J & Roenner, K 1995, 'Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor', Proceedings - IEEE International Symposium on Circuits and Systems, vol. 1, pp. 562-565.
Pirsch, P., Kneip, J., & Roenner, K. (1995). Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor. Proceedings - IEEE International Symposium on Circuits and Systems, 1, 562-565.
Pirsch P, Kneip J, Roenner K. Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor. Proceedings - IEEE International Symposium on Circuits and Systems. 1995;1:562-565.
Pirsch, Peter ; Kneip, Johannes ; Roenner, Karsten. / Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor. In: Proceedings - IEEE International Symposium on Circuits and Systems. 1995 ; Vol. 1. pp. 562-565.
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