Details
| Original language | English |
|---|---|
| Pages (from-to) | 316-319 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 4 |
| Publication status | Published - 1996 |
| Event | 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, United States Duration: 12 May 1996 → 15 May 1996 |
Abstract
The efficient implementation of algorithms with irregular data access or control-flow on a parallel SIMD processor requires specific architectural measures. This paper demonstrates the parallelization of medium-level algorithms on the HiPAR-DSP, a programmable RISC processor for real-time image processing with 4 or 16 parallel data paths. We show the efficient use of memory and ASIMD control capabilities of the processor for the parallel execution of a memory efficient Huffman decoding algorithm. Performance figures for a selection of further medium level algorithms are given, demonstrating that even a SIMD architecture can obtain high utilization for algorithms with data dependent control flow.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
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In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 4, 1996, p. 316-319.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - Parallel implementation of medium level algorithms on a monolithic ASIMD multiprocessor
AU - Kneip, Johannes
AU - Ohmacht, Martin
AU - Wittenburg, Jens Peter
AU - Pirsch, Peter
PY - 1996
Y1 - 1996
N2 - The efficient implementation of algorithms with irregular data access or control-flow on a parallel SIMD processor requires specific architectural measures. This paper demonstrates the parallelization of medium-level algorithms on the HiPAR-DSP, a programmable RISC processor for real-time image processing with 4 or 16 parallel data paths. We show the efficient use of memory and ASIMD control capabilities of the processor for the parallel execution of a memory efficient Huffman decoding algorithm. Performance figures for a selection of further medium level algorithms are given, demonstrating that even a SIMD architecture can obtain high utilization for algorithms with data dependent control flow.
AB - The efficient implementation of algorithms with irregular data access or control-flow on a parallel SIMD processor requires specific architectural measures. This paper demonstrates the parallelization of medium-level algorithms on the HiPAR-DSP, a programmable RISC processor for real-time image processing with 4 or 16 parallel data paths. We show the efficient use of memory and ASIMD control capabilities of the processor for the parallel execution of a memory efficient Huffman decoding algorithm. Performance figures for a selection of further medium level algorithms are given, demonstrating that even a SIMD architecture can obtain high utilization for algorithms with data dependent control flow.
UR - http://www.scopus.com/inward/record.url?scp=0029697178&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0029697178
VL - 4
SP - 316
EP - 319
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
T2 - 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4)
Y2 - 12 May 1996 through 15 May 1996
ER -