Overshoot Prevention in Monolithic GaN by Ultra-Low ESL Gate Loop Design Using Chip-Scale Capacitors and Gate Driver Pull-Up Path Tuning Technique

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Original languageEnglish
Title of host publication2024 IEEE Applied Power Electronics Conference and Exposition
Subtitle of host publicationAPEC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2409-2414
Number of pages6
ISBN (electronic)9798350316643
ISBN (print)979-8-3503-1665-0
Publication statusPublished - 2024
Event39th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2024 - Long Beach, United States
Duration: 25 Feb 202429 Feb 2024

Abstract

Despite monolithic integration of GaN gate drivers with the power stage, some parasitic gate loop inductance remains, including connections to off-chip decoupling capacitors. On-chip capacitors, however, complicate the gate loop design by adding another pole to the system. An LC-RC resonant tank replaces the conventional RLC model, which is insufficient. Ultra-low ESL decoupling using chip-scale silicon capacitors bonded directly to the GaN-IC is identified as most effective by measurements for PCB and bonded MLCC and SiCap gate loop decoupling. A voltage-tuning technique-based gate driver, implemented on a GaN-IC, is applied to adapt to the remaining loop inductance and reduce critical overshoot while ensuring fast switching.

Keywords

    Decoupling, GaN-IC, Gate Driver, Gate Loop, MLCC, Monolithic GaN, SiCap

ASJC Scopus subject areas

Cite this

Overshoot Prevention in Monolithic GaN by Ultra-Low ESL Gate Loop Design Using Chip-Scale Capacitors and Gate Driver Pull-Up Path Tuning Technique. / Deneke, Niklas; Wicht, Bernhard.
2024 IEEE Applied Power Electronics Conference and Exposition: APEC . Institute of Electrical and Electronics Engineers Inc., 2024. p. 2409-2414.

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Deneke, N & Wicht, B 2024, Overshoot Prevention in Monolithic GaN by Ultra-Low ESL Gate Loop Design Using Chip-Scale Capacitors and Gate Driver Pull-Up Path Tuning Technique. in 2024 IEEE Applied Power Electronics Conference and Exposition: APEC . Institute of Electrical and Electronics Engineers Inc., pp. 2409-2414, 39th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2024, Long Beach, California, United States, 25 Feb 2024. https://doi.org/10.1109/APEC48139.2024.10509192
Deneke, N., & Wicht, B. (2024). Overshoot Prevention in Monolithic GaN by Ultra-Low ESL Gate Loop Design Using Chip-Scale Capacitors and Gate Driver Pull-Up Path Tuning Technique. In 2024 IEEE Applied Power Electronics Conference and Exposition: APEC (pp. 2409-2414). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APEC48139.2024.10509192
Deneke N, Wicht B. Overshoot Prevention in Monolithic GaN by Ultra-Low ESL Gate Loop Design Using Chip-Scale Capacitors and Gate Driver Pull-Up Path Tuning Technique. In 2024 IEEE Applied Power Electronics Conference and Exposition: APEC . Institute of Electrical and Electronics Engineers Inc. 2024. p. 2409-2414 doi: 10.1109/APEC48139.2024.10509192
Deneke, Niklas ; Wicht, Bernhard. / Overshoot Prevention in Monolithic GaN by Ultra-Low ESL Gate Loop Design Using Chip-Scale Capacitors and Gate Driver Pull-Up Path Tuning Technique. 2024 IEEE Applied Power Electronics Conference and Exposition: APEC . Institute of Electrical and Electronics Engineers Inc., 2024. pp. 2409-2414
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abstract = "Despite monolithic integration of GaN gate drivers with the power stage, some parasitic gate loop inductance remains, including connections to off-chip decoupling capacitors. On-chip capacitors, however, complicate the gate loop design by adding another pole to the system. An LC-RC resonant tank replaces the conventional RLC model, which is insufficient. Ultra-low ESL decoupling using chip-scale silicon capacitors bonded directly to the GaN-IC is identified as most effective by measurements for PCB and bonded MLCC and SiCap gate loop decoupling. A voltage-tuning technique-based gate driver, implemented on a GaN-IC, is applied to adapt to the remaining loop inductance and reduce critical overshoot while ensuring fast switching.",
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