Details
| Original language | English |
|---|---|
| Title of host publication | 2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 137-141 |
| Number of pages | 5 |
| ISBN (print) | 9781479903504 |
| Publication status | Published - 2013 |
| Event | 2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013 - South Lake Tahoe, CA, United States Duration: 13 Oct 2013 → 17 Oct 2013 |
Publication series
| Name | IEEE International Integrated Reliability Workshop Final Report |
|---|
Abstract
Due to the miniaturization process of the CMOS components metallization structures are becoming more and more complex. Better knowledge to improve via robustness for high current applications is needed. Geometry changes can have a big effect on the physical behaviour. For higher robust metallization systems it is necessary to learn more about overlap design to meet the most economic layout. Slotted high current line layouts do not allow the use of big via areas. Furthermore the number of vias increases the resistance. Investigations have shown the existence of an optimal overlap.
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
- Engineering(all)
- Safety, Risk, Reliability and Quality
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
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2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013. Institute of Electrical and Electronics Engineers Inc., 2013. p. 137-141 6804178 (IEEE International Integrated Reliability Workshop Final Report).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Overlap design for higher tungsten via robustness in AlCu metallizations
AU - Kludt, Jorg
AU - Weide-Zaage, Kirsten
AU - Ackermann, Markus
AU - Hein, Verena
N1 - Copyright: Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2013
Y1 - 2013
N2 - Due to the miniaturization process of the CMOS components metallization structures are becoming more and more complex. Better knowledge to improve via robustness for high current applications is needed. Geometry changes can have a big effect on the physical behaviour. For higher robust metallization systems it is necessary to learn more about overlap design to meet the most economic layout. Slotted high current line layouts do not allow the use of big via areas. Furthermore the number of vias increases the resistance. Investigations have shown the existence of an optimal overlap.
AB - Due to the miniaturization process of the CMOS components metallization structures are becoming more and more complex. Better knowledge to improve via robustness for high current applications is needed. Geometry changes can have a big effect on the physical behaviour. For higher robust metallization systems it is necessary to learn more about overlap design to meet the most economic layout. Slotted high current line layouts do not allow the use of big via areas. Furthermore the number of vias increases the resistance. Investigations have shown the existence of an optimal overlap.
UR - http://www.scopus.com/inward/record.url?scp=84900469353&partnerID=8YFLogxK
U2 - 10.1109/IIRW.2013.6804178
DO - 10.1109/IIRW.2013.6804178
M3 - Conference contribution
AN - SCOPUS:84900469353
SN - 9781479903504
T3 - IEEE International Integrated Reliability Workshop Final Report
SP - 137
EP - 141
BT - 2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013
Y2 - 13 October 2013 through 17 October 2013
ER -