Details
| Original language | English |
|---|---|
| Title of host publication | 2024 Panhellenic Conference on Electronics & Telecommunications (PACET) |
| Pages | 1-5 |
| Number of pages | 5 |
| ISBN (electronic) | 979-8-3503-1884-5 |
| Publication status | Published - 2024 |
Abstract
Modern deep drilling requires a vast array of sensors, actuators and controllers, which are deployed inside the bottom end of the drill string. These electronics are exposed to temperatures up to 175°C and 200MPa of pressure, a so called harsh environment. There is no fast communication to the surface, so in situ digital signal processing is required to operate autonomously. A high-performance RISC-V processor is developed that can operate reliably regardless of the harsh environment. To produce reliable electronic circuits that work under these conditions the XT018 180nm Silicon-on-Insulator (SOI) process from XFAB was chosen as it is one of the state-of-the-art technologies for this harsh environment [1]. Typical RISC-V designs follow the established five-stage pipeline design, but this leaves only one stage for the execution phase, severely limiting the required DSP capabilities. To overcome this limitation, the custom RISC-V processor is equipped with a heterogeneous execution pipeline, resulting in delay differences between units ranging from a single cycle to up to 28 cycles. With this new instruction-dependent pipeline length the RV32IMCF processor is capable of clocking up to 180MHz at 175°C. The synchronization of the asymmetric processor execution stages is accomplished through the use of handshakes, which adds more control logic than usual to each execution unit but offloads the control workload from the controller itself. Compared to an RV32IMFC processor in this technology, which only allows works with a single cycle execution stage, this new design can achieve a clock frequency up to 18 times higher.
Keywords
- ASIC, Controller, Hardware Design, Harsh Environment, High Performance, RISC-V
ASJC Scopus subject areas
- Computer Science(all)
- Signal Processing
- Energy(all)
- Energy Engineering and Power Technology
- Physics and Astronomy(all)
- Instrumentation
- Medicine(all)
- Health Informatics
- Engineering(all)
- Electrical and Electronic Engineering
- Computer Science(all)
- Computer Networks and Communications
Cite this
- Standard
- Harvard
- Apa
- Vancouver
- BibTeX
- RIS
2024 Panhellenic Conference on Electronics & Telecommunications (PACET). 2024. p. 1-5.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Optimizing RISC-V Processor Performance with Adaptive Execution Unit Lengths in Harsh Environment Conditio
AU - Szücs, Jan
AU - Hawich, Malte
AU - Blume, Holger Christoph
PY - 2024
Y1 - 2024
N2 - Modern deep drilling requires a vast array of sensors, actuators and controllers, which are deployed inside the bottom end of the drill string. These electronics are exposed to temperatures up to 175°C and 200MPa of pressure, a so called harsh environment. There is no fast communication to the surface, so in situ digital signal processing is required to operate autonomously. A high-performance RISC-V processor is developed that can operate reliably regardless of the harsh environment. To produce reliable electronic circuits that work under these conditions the XT018 180nm Silicon-on-Insulator (SOI) process from XFAB was chosen as it is one of the state-of-the-art technologies for this harsh environment [1]. Typical RISC-V designs follow the established five-stage pipeline design, but this leaves only one stage for the execution phase, severely limiting the required DSP capabilities. To overcome this limitation, the custom RISC-V processor is equipped with a heterogeneous execution pipeline, resulting in delay differences between units ranging from a single cycle to up to 28 cycles. With this new instruction-dependent pipeline length the RV32IMCF processor is capable of clocking up to 180MHz at 175°C. The synchronization of the asymmetric processor execution stages is accomplished through the use of handshakes, which adds more control logic than usual to each execution unit but offloads the control workload from the controller itself. Compared to an RV32IMFC processor in this technology, which only allows works with a single cycle execution stage, this new design can achieve a clock frequency up to 18 times higher.
AB - Modern deep drilling requires a vast array of sensors, actuators and controllers, which are deployed inside the bottom end of the drill string. These electronics are exposed to temperatures up to 175°C and 200MPa of pressure, a so called harsh environment. There is no fast communication to the surface, so in situ digital signal processing is required to operate autonomously. A high-performance RISC-V processor is developed that can operate reliably regardless of the harsh environment. To produce reliable electronic circuits that work under these conditions the XT018 180nm Silicon-on-Insulator (SOI) process from XFAB was chosen as it is one of the state-of-the-art technologies for this harsh environment [1]. Typical RISC-V designs follow the established five-stage pipeline design, but this leaves only one stage for the execution phase, severely limiting the required DSP capabilities. To overcome this limitation, the custom RISC-V processor is equipped with a heterogeneous execution pipeline, resulting in delay differences between units ranging from a single cycle to up to 28 cycles. With this new instruction-dependent pipeline length the RV32IMCF processor is capable of clocking up to 180MHz at 175°C. The synchronization of the asymmetric processor execution stages is accomplished through the use of handshakes, which adds more control logic than usual to each execution unit but offloads the control workload from the controller itself. Compared to an RV32IMFC processor in this technology, which only allows works with a single cycle execution stage, this new design can achieve a clock frequency up to 18 times higher.
KW - ASIC
KW - Controller
KW - Hardware Design
KW - Harsh Environment
KW - High Performance
KW - RISC-V
UR - http://www.scopus.com/inward/record.url?scp=85191656650&partnerID=8YFLogxK
U2 - 10.1109/PACET60398.2024.10497073
DO - 10.1109/PACET60398.2024.10497073
M3 - Conference contribution
SN - 979-8-3503-1885-2
SP - 1
EP - 5
BT - 2024 Panhellenic Conference on Electronics & Telecommunications (PACET)
ER -