Optimization of chip design processes using task graphs

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Authors

  • Neele Hinrichs
  • Markus Olbrich
  • Erich Barke

Research Organisations

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Details

Original languageEnglish
Title of host publicationICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings
PagesV1116-V1120
Publication statusPublished - 2010
Event2010 2nd International Conference on Software Technology and Engineering, ICSTE 2010 - San Juan, PR, United States
Duration: 3 Oct 20105 Oct 2010

Publication series

NameICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings
Volume1

Abstract

The semiconductor industry is characterized by highly progressive and complex products. Fast technological change and improvement lead to increasing complexity of the design process which makes project scheduling and resource management more and more challenging. The variety of influencing factors makes it complicated to predict the main parameters affecting the project success. In our approach a task graph is generated automatically from design process data to clarify the dependencies between the activities. In a second step, the process and the allocation of resources are optimized and evaluated regarding main objectives as time and cost.

Keywords

    Chip design process, Optimization, Performance measurement, Resource allocation, Scheduling, Task graph

ASJC Scopus subject areas

Cite this

Optimization of chip design processes using task graphs. / Hinrichs, Neele; Olbrich, Markus; Barke, Erich.
ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings. 2010. p. V1116-V1120 5608900 (ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings; Vol. 1).

Research output: Chapter in book/report/conference proceedingConference contributionResearchpeer review

Hinrichs, N, Olbrich, M & Barke, E 2010, Optimization of chip design processes using task graphs. in ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings., 5608900, ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings, vol. 1, pp. V1116-V1120, 2010 2nd International Conference on Software Technology and Engineering, ICSTE 2010, San Juan, PR, United States, 3 Oct 2010. https://doi.org/10.1109/ICSTE.2010.5608900
Hinrichs, N., Olbrich, M., & Barke, E. (2010). Optimization of chip design processes using task graphs. In ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings (pp. V1116-V1120). Article 5608900 (ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings; Vol. 1). https://doi.org/10.1109/ICSTE.2010.5608900
Hinrichs N, Olbrich M, Barke E. Optimization of chip design processes using task graphs. In ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings. 2010. p. V1116-V1120. 5608900. (ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings). doi: 10.1109/ICSTE.2010.5608900
Hinrichs, Neele ; Olbrich, Markus ; Barke, Erich. / Optimization of chip design processes using task graphs. ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings. 2010. pp. V1116-V1120 (ICSTE 2010 - 2010 2nd International Conference on Software Technology and Engineering, Proceedings).
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