On the design of scalable massively parallel CRC circuits

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

Authors

  • Konstantin Septinus
  • Thuyen Le
  • Ulrich Mayer
  • Peter Pirsch

Research Organisations

External Research Organisations

  • IBM
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Details

Original languageEnglish
Title of host publicationICECS 2007
Subtitle of host publication14th IEEE International Conference on Electronics, Circuits and Systems
Pages142-145
Number of pages4
Publication statusPublished - 2007
Event14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
Duration: 11 Dec 2007 → 14 Dec 2007

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Abstract

This paper presents a scalable massively parallel CRC architecture for high-speed network processing. The proposed method considers wide data busses, which result in highest throughput. In addition, data streams are processed without interrupts. An investigated 65nm-ASIC implementation example for 32-bit CRC encoding operates on 58 GBps data streams at reasonable costs (0.036 mm 2). The proposed method can be exploited furthermore in order to develop a configurable circuit for a group of generator polynomials, without the requirement of fully programmable architecture.

ASJC Scopus subject areas

Cite this

On the design of scalable massively parallel CRC circuits. / Septinus, Konstantin; Le, Thuyen; Mayer, Ulrich et al.
ICECS 2007 : 14th IEEE International Conference on Electronics, Circuits and Systems. 2007. p. 142-145 4510950 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review

Septinus, K, Le, T, Mayer, U & Pirsch, P 2007, On the design of scalable massively parallel CRC circuits. in ICECS 2007 : 14th IEEE International Conference on Electronics, Circuits and Systems., 4510950, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 142-145, 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007, Marrakech, Morocco, 11 Dec 2007. https://doi.org/10.1109/ICECS.2007.4510950
Septinus, K., Le, T., Mayer, U., & Pirsch, P. (2007). On the design of scalable massively parallel CRC circuits. In ICECS 2007 : 14th IEEE International Conference on Electronics, Circuits and Systems (pp. 142-145). Article 4510950 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). https://doi.org/10.1109/ICECS.2007.4510950
Septinus K, Le T, Mayer U, Pirsch P. On the design of scalable massively parallel CRC circuits. In ICECS 2007 : 14th IEEE International Conference on Electronics, Circuits and Systems. 2007. p. 142-145. 4510950. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.2007.4510950
Septinus, Konstantin ; Le, Thuyen ; Mayer, Ulrich et al. / On the design of scalable massively parallel CRC circuits. ICECS 2007 : 14th IEEE International Conference on Electronics, Circuits and Systems. 2007. pp. 142-145 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).
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