Details
| Original language | English |
|---|---|
| Pages (from-to) | 241-250 |
| Number of pages | 10 |
| Journal | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |
| Publication status | Published - 1999 |
| Event | 1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation' - Taipei, Taiwan Duration: 20 Oct 1999 → 22 Oct 1999 |
Abstract
Starting from an evaluation of recent and future image processing algorithm's properties, this paper proposes a new class of parallel DSP architectures adapting the concept of simultaneous multithreading (SMT) to signal processing applications. This concept allows to enable parallelization resources on thread level, which are unused by most recent media-processors and video-DSPs. A customizable simulator to explore the architecture's parameters dependent on algorithmic properties and implementation constraints is presented. Coarse estimations for the realization costs in terms of silicon area are derived. First simulated performance figures for selected image processing algorithms show that SMT architectures are suitable to increase the processor's overall utilization and can achieve a speed-up beyond the limits of VLIW and superscalar architectures.
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In: IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 1999, p. 241-250.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - Multithreaded architecture approach to parallel DSPs for high performance image processing applications
AU - Wittenburg, Jens Peter
AU - Pirsch, Peter
AU - Meyer, Gerald
PY - 1999
Y1 - 1999
N2 - Starting from an evaluation of recent and future image processing algorithm's properties, this paper proposes a new class of parallel DSP architectures adapting the concept of simultaneous multithreading (SMT) to signal processing applications. This concept allows to enable parallelization resources on thread level, which are unused by most recent media-processors and video-DSPs. A customizable simulator to explore the architecture's parameters dependent on algorithmic properties and implementation constraints is presented. Coarse estimations for the realization costs in terms of silicon area are derived. First simulated performance figures for selected image processing algorithms show that SMT architectures are suitable to increase the processor's overall utilization and can achieve a speed-up beyond the limits of VLIW and superscalar architectures.
AB - Starting from an evaluation of recent and future image processing algorithm's properties, this paper proposes a new class of parallel DSP architectures adapting the concept of simultaneous multithreading (SMT) to signal processing applications. This concept allows to enable parallelization resources on thread level, which are unused by most recent media-processors and video-DSPs. A customizable simulator to explore the architecture's parameters dependent on algorithmic properties and implementation constraints is presented. Coarse estimations for the realization costs in terms of silicon area are derived. First simulated performance figures for selected image processing algorithms show that SMT architectures are suitable to increase the processor's overall utilization and can achieve a speed-up beyond the limits of VLIW and superscalar architectures.
UR - http://www.scopus.com/inward/record.url?scp=0033332050&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0033332050
SP - 241
EP - 250
JO - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
JF - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SN - 1520-6130
T2 - 1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation'
Y2 - 20 October 1999 through 22 October 1999
ER -