Details
| Original language | English |
|---|---|
| Title of host publication | 2023 IEEE 29th Real-Time and Embedded Technology and Applications Symposium |
| Subtitle of host publication | RTAS |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 262-275 |
| Number of pages | 14 |
| ISBN (electronic) | 9798350321760 |
| ISBN (print) | 979-8-3503-2177-7 |
| Publication status | Published - 2023 |
| Event | 29th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2023 - San Antonio, United States Duration: 9 May 2023 → 12 May 2023 |
Publication series
| Name | Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS |
|---|---|
| Volume | 2023-May |
| ISSN (Print) | 1545-3421 |
Abstract
The implementation of static real-time control systems often allows for extensive compile-time optimizations based on RTOS-aware whole-program analyses. Previous work has shown the high optimization potential of control-flow aware static system-call tailoring, but is restricted to single-core systems due to the inherent problem of an exponentially growing analysis state in multicore settings. We present MultiSSE, a multi-core capable and RTOS-aware static whole-system analysis that makes such analyses also feasible on multi-core systems. MultiSSE exploits structural and optional timing information to analyze the core-level control flows as independently as possible from each other, synchronizing their states only when necessary. Thereby, MultiSSE provides means to realize compile-time deadlock detection, lock elision, and systemcall optimization also on multi-core systems. We evaluate our approach with synthetic benchmarks and a real-world quadrotor application. In all cases, we were able to optimize or even completely elide costly cross-core system calls and system objects.
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2023 IEEE 29th Real-Time and Embedded Technology and Applications Symposium: RTAS. Institute of Electrical and Electronics Engineers Inc., 2023. p. 262-275 (Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS; Vol. 2023-May).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - MultiSSE
T2 - 29th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2023
AU - Entrup, Gerion
AU - Fiedler, Bjorn
AU - Lohmann, Daniel
PY - 2023
Y1 - 2023
N2 - The implementation of static real-time control systems often allows for extensive compile-time optimizations based on RTOS-aware whole-program analyses. Previous work has shown the high optimization potential of control-flow aware static system-call tailoring, but is restricted to single-core systems due to the inherent problem of an exponentially growing analysis state in multicore settings. We present MultiSSE, a multi-core capable and RTOS-aware static whole-system analysis that makes such analyses also feasible on multi-core systems. MultiSSE exploits structural and optional timing information to analyze the core-level control flows as independently as possible from each other, synchronizing their states only when necessary. Thereby, MultiSSE provides means to realize compile-time deadlock detection, lock elision, and systemcall optimization also on multi-core systems. We evaluate our approach with synthetic benchmarks and a real-world quadrotor application. In all cases, we were able to optimize or even completely elide costly cross-core system calls and system objects.
AB - The implementation of static real-time control systems often allows for extensive compile-time optimizations based on RTOS-aware whole-program analyses. Previous work has shown the high optimization potential of control-flow aware static system-call tailoring, but is restricted to single-core systems due to the inherent problem of an exponentially growing analysis state in multicore settings. We present MultiSSE, a multi-core capable and RTOS-aware static whole-system analysis that makes such analyses also feasible on multi-core systems. MultiSSE exploits structural and optional timing information to analyze the core-level control flows as independently as possible from each other, synchronizing their states only when necessary. Thereby, MultiSSE provides means to realize compile-time deadlock detection, lock elision, and systemcall optimization also on multi-core systems. We evaluate our approach with synthetic benchmarks and a real-world quadrotor application. In all cases, we were able to optimize or even completely elide costly cross-core system calls and system objects.
KW - multi core
KW - optimization
KW - RTOS
KW - static analysis
UR - http://www.scopus.com/inward/record.url?scp=85164540238&partnerID=8YFLogxK
U2 - 10.1109/RTAS58335.2023.00028
DO - 10.1109/RTAS58335.2023.00028
M3 - Conference contribution
AN - SCOPUS:85164540238
SN - 979-8-3503-2177-7
T3 - Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS
SP - 262
EP - 275
BT - 2023 IEEE 29th Real-Time and Embedded Technology and Applications Symposium
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 May 2023 through 12 May 2023
ER -