Details
| Original language | English |
|---|---|
| Pages (from-to) | 688-699 |
| Number of pages | 12 |
| Journal | IEEE Transactions on Circuits and Systems for Video Technology |
| Volume | 12 |
| Issue number | 8 |
| Publication status | Published - Aug 2002 |
Abstract
The newly defined MPEG-4 Advanced Simple (AS) profile delivers single-layered streaming video in digital television (DTV) quality in the promising 1-2 Mbit/s range. However, the coding tools involved add significantly to the complexity of the decoding process, raising the need for further hardware acceleration. A programmable multicore system-on-chip (SOC) architecture is presented which targets MPEG-4 AS profile decoding of ITU-R 601 resolution streaming video. Based on a detailed analysis of corresponding bitstream statistics, the implementation of an optimized software video decoder for the proposed architecture is described. Results show that overall performance is sufficient for real-time AS profile decoding of ITU-R 601 resolution video.
Keywords
- Computer architecture, Digital signal processors, Very-large-scale integration, Video signal processing
ASJC Scopus subject areas
- Engineering(all)
- Media Technology
- Engineering(all)
- Electrical and Electronic Engineering
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In: IEEE Transactions on Circuits and Systems for Video Technology, Vol. 12, No. 8, 08.2002, p. 688-699.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Multicore system-on-chip architecture for MPEG-4 streaming video
AU - Bereković, Mladen
AU - Stolberg, Hans Joachim
AU - Pirsch, Peter
N1 - Funding Information: Manuscript received December 2001; revised April 8, 2002. This work was supported in part by the European MEDEA M4M Project through Robert Bosch GmbH, Hildesheim, Germany. The authors are with the Institute of Microelectronic Circuits and Systems, University of Hannover, 30167 Hannover, Germany (e-mail: berekov@ims.uni-hannover.de). Publisher Item Identifier 10.1109/TCSVT.2002.800860.
PY - 2002/8
Y1 - 2002/8
N2 - The newly defined MPEG-4 Advanced Simple (AS) profile delivers single-layered streaming video in digital television (DTV) quality in the promising 1-2 Mbit/s range. However, the coding tools involved add significantly to the complexity of the decoding process, raising the need for further hardware acceleration. A programmable multicore system-on-chip (SOC) architecture is presented which targets MPEG-4 AS profile decoding of ITU-R 601 resolution streaming video. Based on a detailed analysis of corresponding bitstream statistics, the implementation of an optimized software video decoder for the proposed architecture is described. Results show that overall performance is sufficient for real-time AS profile decoding of ITU-R 601 resolution video.
AB - The newly defined MPEG-4 Advanced Simple (AS) profile delivers single-layered streaming video in digital television (DTV) quality in the promising 1-2 Mbit/s range. However, the coding tools involved add significantly to the complexity of the decoding process, raising the need for further hardware acceleration. A programmable multicore system-on-chip (SOC) architecture is presented which targets MPEG-4 AS profile decoding of ITU-R 601 resolution streaming video. Based on a detailed analysis of corresponding bitstream statistics, the implementation of an optimized software video decoder for the proposed architecture is described. Results show that overall performance is sufficient for real-time AS profile decoding of ITU-R 601 resolution video.
KW - Computer architecture
KW - Digital signal processors
KW - Very-large-scale integration
KW - Video signal processing
UR - http://www.scopus.com/inward/record.url?scp=0036686464&partnerID=8YFLogxK
U2 - 10.1109/TCSVT.2002.800860
DO - 10.1109/TCSVT.2002.800860
M3 - Article
AN - SCOPUS:0036686464
VL - 12
SP - 688
EP - 699
JO - IEEE Transactions on Circuits and Systems for Video Technology
JF - IEEE Transactions on Circuits and Systems for Video Technology
SN - 1051-8215
IS - 8
ER -