Details
| Original language | English |
|---|---|
| Article number | 1717490 |
| Pages (from-to) | 408-420 |
| Number of pages | 13 |
| Journal | IEEE Transactions on Device and Materials Reliability |
| Volume | 6 |
| Issue number | 3 |
| Publication status | Published - Sept 2006 |
Abstract
Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. In order to indicate inadmissible substrate currents and to evaluate protection measures, these parasitic transistors have to be included into a postlayout simulation. A methodology has been developed for automatically generating Verilog-A models for these parasites from layout data. These models account for an inhomogeneous current flow and high electron densities in the substrate. A reasonable tradeoff between convergence behavior and accuracy of the model has been found.
Keywords
- Bipolar transistors, Nonlinearities, Numerical stability, Power system simulation, Semiconductor device modeling
ASJC Scopus subject areas
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Engineering(all)
- Safety, Risk, Reliability and Quality
- Engineering(all)
- Electrical and Electronic Engineering
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In: IEEE Transactions on Device and Materials Reliability, Vol. 6, No. 3, 1717490, 09.2006, p. 408-420.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Modeling lateral parasitic transistors in smart power ICs
AU - Oehmen, Joerg
AU - Olbrich, Markus
AU - Hedrich, Lars
AU - Barke, Erich
PY - 2006/9
Y1 - 2006/9
N2 - Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. In order to indicate inadmissible substrate currents and to evaluate protection measures, these parasitic transistors have to be included into a postlayout simulation. A methodology has been developed for automatically generating Verilog-A models for these parasites from layout data. These models account for an inhomogeneous current flow and high electron densities in the substrate. A reasonable tradeoff between convergence behavior and accuracy of the model has been found.
AB - Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. In order to indicate inadmissible substrate currents and to evaluate protection measures, these parasitic transistors have to be included into a postlayout simulation. A methodology has been developed for automatically generating Verilog-A models for these parasites from layout data. These models account for an inhomogeneous current flow and high electron densities in the substrate. A reasonable tradeoff between convergence behavior and accuracy of the model has been found.
KW - Bipolar transistors
KW - Nonlinearities
KW - Numerical stability
KW - Power system simulation
KW - Semiconductor device modeling
UR - http://www.scopus.com/inward/record.url?scp=33750842991&partnerID=8YFLogxK
U2 - 10.1109/TDMR.2006.881506
DO - 10.1109/TDMR.2006.881506
M3 - Article
AN - SCOPUS:33750842991
VL - 6
SP - 408
EP - 420
JO - IEEE Transactions on Device and Materials Reliability
JF - IEEE Transactions on Device and Materials Reliability
SN - 1530-4388
IS - 3
M1 - 1717490
ER -