Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 29-40 |
| Number of pages | 12 |
| ISBN (print) | 0-7695-1712-9 |
| Publication status | Published - 7 Nov 2002 |
| Externally published | Yes |
Abstract
The exploration of the design space for heterogeneous reconfigurable systems on chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks, ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Therefore, the goal of this work is to provide estimations of implementation specific parameters like throughput rate, power dissipation and silicon area by means of cost functions. A concept for a model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to prove the feasibility of this exploration strategy, first of all operations were implemented on discrete components like DSPs, FPGAs or dedicated ASICs. Implementation parameters are provided for a variety of basic operations frequently required in digital signal processing. These implementation parameters serve as a basis for deriving models for the design space exploration concept.
Keywords
- Cost function, Digital signal processing, Field programmable gate arrays, Power dissipation, Process design, Silicon, Space exploration, System-on-a-chip, Technological innovation, Throughput
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Computer Science(all)
- Computer Networks and Communications
Cite this
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Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors. Institute of Electrical and Electronics Engineers Inc., 2002. p. 29-40.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Model-based exploration of the design space for heterogeneous systems on chip
AU - Blume, H.
AU - Hubert, H.
AU - Feldkämper, H. T.
AU - Noll, T. G.
PY - 2002/11/7
Y1 - 2002/11/7
N2 - The exploration of the design space for heterogeneous reconfigurable systems on chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks, ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Therefore, the goal of this work is to provide estimations of implementation specific parameters like throughput rate, power dissipation and silicon area by means of cost functions. A concept for a model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to prove the feasibility of this exploration strategy, first of all operations were implemented on discrete components like DSPs, FPGAs or dedicated ASICs. Implementation parameters are provided for a variety of basic operations frequently required in digital signal processing. These implementation parameters serve as a basis for deriving models for the design space exploration concept.
AB - The exploration of the design space for heterogeneous reconfigurable systems on chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks, ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Therefore, the goal of this work is to provide estimations of implementation specific parameters like throughput rate, power dissipation and silicon area by means of cost functions. A concept for a model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to prove the feasibility of this exploration strategy, first of all operations were implemented on discrete components like DSPs, FPGAs or dedicated ASICs. Implementation parameters are provided for a variety of basic operations frequently required in digital signal processing. These implementation parameters serve as a basis for deriving models for the design space exploration concept.
KW - Cost function
KW - Digital signal processing
KW - Field programmable gate arrays
KW - Power dissipation
KW - Process design
KW - Silicon
KW - Space exploration
KW - System-on-a-chip
KW - Technological innovation
KW - Throughput
UR - http://www.scopus.com/inward/record.url?scp=84882411795&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2002.1030702
DO - 10.1109/ASAP.2002.1030702
M3 - Conference contribution
AN - SCOPUS:84882411795
SN - 0-7695-1712-9
SP - 29
EP - 40
BT - Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors
PB - Institute of Electrical and Electronics Engineers Inc.
ER -