TY - GEN

T1 - MHz-converter design for high conversion ratio

AU - Wittmann, Juergen

AU - Wicht, Bernhard

N1 - Copyright: Copyright 2014 Elsevier B.V., All rights reserved.

PY - 2013

Y1 - 2013

N2 - This paper presents a circuit design and efficiency study for integrated converters with switching frequencies up to 15 MHz at high conversion ratio with input voltages up to 40 V and output voltages <5 V. An asynchronous buck converter is well suitable, while in contrast, a synchronous topology causes larger switching losses due to its low side switch. Critical design aspects are presented along with an implementation in a 180 nm HV BiCMOS technology. A saw-tooth with fast fall time is achieved with two interleaved integrator stages. The limitation due to the finite fall-time of the saw tooth signal was solved by a PWM comparator that gets reset by a synchronized clock with an adjusted lead time at min. or max. duty cycle, respectively. A high speed level shifter is used to shift the PWM signal to the high side domain. The gate driver uses a two-branch tapered buffer with asymmetry factor to achieve maximum switching speed while at the same time the current consumption is minimized. An efficiency model, verified by measurements, allows to simulate and to determine quantitatively the root cause of the power losses separately for each circuit block. At 15 MHz and 10 V input voltage a peak efficiency of ∼65 % was achieved. While the efficiency reduces to about 35 % for a conversion from 40 V input to 5 V output, resonant concepts are expected to reach >50 % efficiency. In experiments a switching frequency of 40 MHz was achieved.

AB - This paper presents a circuit design and efficiency study for integrated converters with switching frequencies up to 15 MHz at high conversion ratio with input voltages up to 40 V and output voltages <5 V. An asynchronous buck converter is well suitable, while in contrast, a synchronous topology causes larger switching losses due to its low side switch. Critical design aspects are presented along with an implementation in a 180 nm HV BiCMOS technology. A saw-tooth with fast fall time is achieved with two interleaved integrator stages. The limitation due to the finite fall-time of the saw tooth signal was solved by a PWM comparator that gets reset by a synchronized clock with an adjusted lead time at min. or max. duty cycle, respectively. A high speed level shifter is used to shift the PWM signal to the high side domain. The gate driver uses a two-branch tapered buffer with asymmetry factor to achieve maximum switching speed while at the same time the current consumption is minimized. An efficiency model, verified by measurements, allows to simulate and to determine quantitatively the root cause of the power losses separately for each circuit block. At 15 MHz and 10 V input voltage a peak efficiency of ∼65 % was achieved. While the efficiency reduces to about 35 % for a conversion from 40 V input to 5 V output, resonant concepts are expected to reach >50 % efficiency. In experiments a switching frequency of 40 MHz was achieved.

UR - http://www.scopus.com/inward/record.url?scp=84893223197&partnerID=8YFLogxK

U2 - 10.1109/ISPSD.2013.6694445

DO - 10.1109/ISPSD.2013.6694445

M3 - Conference contribution

AN - SCOPUS:84893223197

SN - 9781467351348

T3 - Proceedings of the International Symposium on Power Semiconductor Devices and ICs

SP - 127

EP - 130

BT - 2013 25th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2013

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2013 25th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2013

Y2 - 26 May 2013 through 30 May 2013

ER -