Details
| Original language | English |
|---|---|
| Title of host publication | Proceedings - IEEE International SOC Conference, SOCC 2009 |
| Pages | 427-431 |
| Number of pages | 5 |
| Publication status | Published - 2009 |
| Event | IEEE International SOC Conference, SOCC 2009 - Belfast, Ireland Duration: 9 Sept 2009 → 11 Sept 2009 |
Publication series
| Name | Proceedings - IEEE International SOC Conference, SOCC 2009 |
|---|
Abstract
Decoding of high bitrate video bitstreams is an application field traditionally claimed by dedicated hardware architectures, since embedded general purpose processors are not able to satisfy the high performance requirements of entropy decoding. We present a fully programmable multi-standard bitstream processor. The proposed bit granular memory and data path architecture provides efficient processing and storage capabilities for data words of arbitrary length. Running at a 300 MHz clock frequency, the processor is able to decode, e.g., MPEG-2 and VC-1 1080p HDTV bitstreams with a maximum bitrate of 100 Mbit/s.
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Electrical and Electronic Engineering
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Proceedings - IEEE International SOC Conference, SOCC 2009. 2009. p. 427-431 5398001 (Proceedings - IEEE International SOC Conference, SOCC 2009).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams
AU - Nolte, N.
AU - Moch, S.
AU - Kock, M.
AU - Pirsch, P.
PY - 2009
Y1 - 2009
N2 - Decoding of high bitrate video bitstreams is an application field traditionally claimed by dedicated hardware architectures, since embedded general purpose processors are not able to satisfy the high performance requirements of entropy decoding. We present a fully programmable multi-standard bitstream processor. The proposed bit granular memory and data path architecture provides efficient processing and storage capabilities for data words of arbitrary length. Running at a 300 MHz clock frequency, the processor is able to decode, e.g., MPEG-2 and VC-1 1080p HDTV bitstreams with a maximum bitrate of 100 Mbit/s.
AB - Decoding of high bitrate video bitstreams is an application field traditionally claimed by dedicated hardware architectures, since embedded general purpose processors are not able to satisfy the high performance requirements of entropy decoding. We present a fully programmable multi-standard bitstream processor. The proposed bit granular memory and data path architecture provides efficient processing and storage capabilities for data words of arbitrary length. Running at a 300 MHz clock frequency, the processor is able to decode, e.g., MPEG-2 and VC-1 1080p HDTV bitstreams with a maximum bitrate of 100 Mbit/s.
UR - http://www.scopus.com/inward/record.url?scp=77949589076&partnerID=8YFLogxK
U2 - 10.1109/SOCCON.2009.5398001
DO - 10.1109/SOCCON.2009.5398001
M3 - Conference contribution
AN - SCOPUS:77949589076
SN - 9781424452200
T3 - Proceedings - IEEE International SOC Conference, SOCC 2009
SP - 427
EP - 431
BT - Proceedings - IEEE International SOC Conference, SOCC 2009
T2 - IEEE International SOC Conference, SOCC 2009
Y2 - 9 September 2009 through 11 September 2009
ER -