Details
| Original language | English |
|---|---|
| Pages (from-to) | 67-78 |
| Number of pages | 12 |
| Journal | Proceedings of SPIE - The International Society for Optical Engineering |
| Volume | 3311 |
| Publication status | Published - 26 Mar 1998 |
| Event | Multimedia Hardware Architectures 1998 - San Jose, CA, United States Duration: 29 Jan 1998 → 30 Jan 1998 |
Abstract
When implementing today's video compression standards on programmable processors, it is essential to optimize the algorithms with respect to the underlying hardware. As an example, the core decoder functions of the H.263 hybrid coding scheme were implemented on a SIMD controlled processor with four parallel VLIW data paths, the HiPAR-DSP. The decoder tasks were implemented employing local memory, parallelization on several levels, and data statistics. Special effort was paid on the computation intensive tasks IDCT, and motion compensated frame reconstruction. To speed up the IDCT computation, a data dependent approach was chosen, which distinguishes different block types. The determination of IDCT block type could be parallelized together with other tasks, thus no additional overhead is required. Frame reconstruction mainly benefits from data parallel operations and transparent DMA transfers to and from external memory.
Keywords
- Algorithm mapping, H.263, MPEG, Parallelization techniques, SIMD, Video decoding
ASJC Scopus subject areas
- Materials Science(all)
- Electronic, Optical and Magnetic Materials
- Physics and Astronomy(all)
- Condensed Matter Physics
- Computer Science(all)
- Computer Science Applications
- Mathematics(all)
- Applied Mathematics
- Engineering(all)
- Electrical and Electronic Engineering
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In: Proceedings of SPIE - The International Society for Optical Engineering, Vol. 3311, 26.03.1998, p. 67-78.
Research output: Contribution to journal › Conference article › Research › peer review
}
TY - JOUR
T1 - Mapping of video decoder software on a VLIW DSP multiprocessor
AU - Freimann, Achim
AU - Brune, Thomas
AU - Pirsch, Peter
PY - 1998/3/26
Y1 - 1998/3/26
N2 - When implementing today's video compression standards on programmable processors, it is essential to optimize the algorithms with respect to the underlying hardware. As an example, the core decoder functions of the H.263 hybrid coding scheme were implemented on a SIMD controlled processor with four parallel VLIW data paths, the HiPAR-DSP. The decoder tasks were implemented employing local memory, parallelization on several levels, and data statistics. Special effort was paid on the computation intensive tasks IDCT, and motion compensated frame reconstruction. To speed up the IDCT computation, a data dependent approach was chosen, which distinguishes different block types. The determination of IDCT block type could be parallelized together with other tasks, thus no additional overhead is required. Frame reconstruction mainly benefits from data parallel operations and transparent DMA transfers to and from external memory.
AB - When implementing today's video compression standards on programmable processors, it is essential to optimize the algorithms with respect to the underlying hardware. As an example, the core decoder functions of the H.263 hybrid coding scheme were implemented on a SIMD controlled processor with four parallel VLIW data paths, the HiPAR-DSP. The decoder tasks were implemented employing local memory, parallelization on several levels, and data statistics. Special effort was paid on the computation intensive tasks IDCT, and motion compensated frame reconstruction. To speed up the IDCT computation, a data dependent approach was chosen, which distinguishes different block types. The determination of IDCT block type could be parallelized together with other tasks, thus no additional overhead is required. Frame reconstruction mainly benefits from data parallel operations and transparent DMA transfers to and from external memory.
KW - Algorithm mapping
KW - H.263
KW - MPEG
KW - Parallelization techniques
KW - SIMD
KW - Video decoding
UR - http://www.scopus.com/inward/record.url?scp=0032387902&partnerID=8YFLogxK
U2 - 10.1117/12.304662
DO - 10.1117/12.304662
M3 - Conference article
AN - SCOPUS:0032387902
VL - 3311
SP - 67
EP - 78
JO - Proceedings of SPIE - The International Society for Optical Engineering
JF - Proceedings of SPIE - The International Society for Optical Engineering
SN - 0277-786X
T2 - Multimedia Hardware Architectures 1998
Y2 - 29 January 1998 through 30 January 1998
ER -