Details
| Original language | English |
|---|---|
| Title of host publication | Custom Integrated Circuits Conference (CICC) |
| Pages | 1-5 |
| ISBN (electronic) | 9781728160313 |
| Publication status | Published - 2020 |
Publication series
| Name | Proceedings of the Custom Integrated Circuits Conference |
|---|---|
| Volume | 2020-March |
| ISSN (Print) | 0886-5930 |
Abstract
With fast switching GaN any parasitic gate loop inductance degrades the switching performance and may lead to false turn-on as well as gate voltage overshoot. Two approaches to overcome these challenges in driving GaN transistors are discussed in this paper. In a discrete silicon based driver, the gate loop inductance is actively utilized for a resonant gate drive approach. In a second implementation, the gate loop inductance is reduced close to zero by GaN-on-Si monolithic integration of the power transistor and the driver on one die. It includes an integrated supply voltage regulator circuit that generates the gate drive voltage out of the high-voltage switching node. The results show fast and robust switching behavior with minimal ringing.
Keywords
- GaN, drivers, gate loop inductance, high dV/dt slew rate, robust switching
ASJC Scopus subject areas
- Engineering(all)
- Electrical and Electronic Engineering
Cite this
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Custom Integrated Circuits Conference (CICC) . 2020. p. 1-5 9075937 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2020-March).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Long, Short, Monolithic - The Gate Loop Challenge for GaN Drivers - Invited Paper.
AU - Kaufmann, Maik
AU - Seidel, Achim
AU - Wicht, Bernhard
PY - 2020
Y1 - 2020
N2 - With fast switching GaN any parasitic gate loop inductance degrades the switching performance and may lead to false turn-on as well as gate voltage overshoot. Two approaches to overcome these challenges in driving GaN transistors are discussed in this paper. In a discrete silicon based driver, the gate loop inductance is actively utilized for a resonant gate drive approach. In a second implementation, the gate loop inductance is reduced close to zero by GaN-on-Si monolithic integration of the power transistor and the driver on one die. It includes an integrated supply voltage regulator circuit that generates the gate drive voltage out of the high-voltage switching node. The results show fast and robust switching behavior with minimal ringing.
AB - With fast switching GaN any parasitic gate loop inductance degrades the switching performance and may lead to false turn-on as well as gate voltage overshoot. Two approaches to overcome these challenges in driving GaN transistors are discussed in this paper. In a discrete silicon based driver, the gate loop inductance is actively utilized for a resonant gate drive approach. In a second implementation, the gate loop inductance is reduced close to zero by GaN-on-Si monolithic integration of the power transistor and the driver on one die. It includes an integrated supply voltage regulator circuit that generates the gate drive voltage out of the high-voltage switching node. The results show fast and robust switching behavior with minimal ringing.
KW - GaN
KW - drivers
KW - gate loop inductance
KW - high dV/dt slew rate
KW - robust switching
UR - http://www.scopus.com/inward/record.url?scp=85084453476&partnerID=8YFLogxK
U2 - 10.1109/cicc48029.2020.9075937
DO - 10.1109/cicc48029.2020.9075937
M3 - Conference contribution
SN - 978-1-7281-6032-0
T3 - Proceedings of the Custom Integrated Circuits Conference
SP - 1
EP - 5
BT - Custom Integrated Circuits Conference (CICC)
ER -