Kerfless epitaxial silicon wafers with 7ms carrier lifetimes and a wide lift-off process window

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Authors

  • Catherin Gemmel
  • Jan Hensen
  • Lasse David
  • Sarah Kajari-Schröder
  • Rolf Brendel

Research Organisations

External Research Organisations

  • Institute for Solar Energy Research (ISFH)
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Details

Original languageEnglish
Article number041301
JournalJapanese Journal of Applied Physics
Volume57
Issue number4
Early online date22 Feb 2018
Publication statusPublished - Apr 2018

Abstract

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm%3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

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Cite this

Kerfless epitaxial silicon wafers with 7ms carrier lifetimes and a wide lift-off process window. / Gemmel, Catherin; Hensen, Jan; David, Lasse et al.
In: Japanese Journal of Applied Physics, Vol. 57, No. 4, 041301, 04.2018.

Research output: Contribution to journalArticleResearchpeer review

Gemmel C, Hensen J, David L, Kajari-Schröder S, Brendel R. Kerfless epitaxial silicon wafers with 7ms carrier lifetimes and a wide lift-off process window. Japanese Journal of Applied Physics. 2018 Apr;57(4):041301. Epub 2018 Feb 22. doi: 10.7567/JJAP.57.041301
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@article{dba2029bf5d543a88f5962a898161106,
title = "Kerfless epitaxial silicon wafers with 7ms carrier lifetimes and a wide lift-off process window",
abstract = "Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm%3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.",
author = "Catherin Gemmel and Jan Hensen and Lasse David and Sarah Kajari-Schr{\"o}der and Rolf Brendel",
note = "Publisher Copyright: {\textcopyright} 2018 The Japan Society of Applied Physics. Copyright: Copyright 2018 Elsevier B.V., All rights reserved.",
year = "2018",
month = apr,
doi = "10.7567/JJAP.57.041301",
language = "English",
volume = "57",
journal = "Japanese Journal of Applied Physics",
issn = "0021-4922",
publisher = "Japan Society of Applied Physics",
number = "4",

}

Download

TY - JOUR

T1 - Kerfless epitaxial silicon wafers with 7ms carrier lifetimes and a wide lift-off process window

AU - Gemmel, Catherin

AU - Hensen, Jan

AU - David, Lasse

AU - Kajari-Schröder, Sarah

AU - Brendel, Rolf

N1 - Publisher Copyright: © 2018 The Japan Society of Applied Physics. Copyright: Copyright 2018 Elsevier B.V., All rights reserved.

PY - 2018/4

Y1 - 2018/4

N2 - Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm%3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

AB - Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm%3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

UR - http://www.scopus.com/inward/record.url?scp=85044421084&partnerID=8YFLogxK

U2 - 10.7567/JJAP.57.041301

DO - 10.7567/JJAP.57.041301

M3 - Article

AN - SCOPUS:85044421084

VL - 57

JO - Japanese Journal of Applied Physics

JF - Japanese Journal of Applied Physics

SN - 0021-4922

IS - 4

M1 - 041301

ER -