Details
| Original language | English |
|---|---|
| Title of host publication | 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) |
| Subtitle of host publication | Proceedings |
| Editors | Carolina Metzler, Giovanni De Micheli, Pierre-Emmanuel Gaillardon, Carlos Silva-Cardenas, Ricardo Reis |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 99-104 |
| Number of pages | 6 |
| ISBN (electronic) | 978-1-7281-3915-9 |
| ISBN (print) | 978-1-7281-3916-6 |
| Publication status | Published - Oct 2019 |
| Event | 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 - Cuzco, Peru Duration: 6 Oct 2019 → 9 Oct 2019 |
Publication series
| Name | International Conference on VLSI and System-on-Chip |
|---|---|
| ISSN (Print) | 2324-8432 |
| ISSN (electronic) | 2324-8440 |
Abstract
Keywords
- asic, asip, hearing aid, low-power, processor, system on chip
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Computer Science(all)
- Software
- Engineering(all)
- Electrical and Electronic Engineering
Sustainable Development Goals
Cite this
- Standard
- Harvard
- Apa
- Vancouver
- BibTeX
- RIS
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC): Proceedings. ed. / Carolina Metzler; Giovanni De Micheli; Pierre-Emmanuel Gaillardon; Carlos Silva-Cardenas; Ricardo Reis. Institute of Electrical and Electronics Engineers Inc., 2019. p. 99-104 8920354 (International Conference on VLSI and System-on-Chip).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - KAVUAKA
T2 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019
AU - Gerlach, Lukas
AU - Paya-Vaya, Guillermo
AU - Blume, Holger
N1 - Funding information: This work was funded by the Deutsche Forschungsgemein-schaft (DFG, German Research Foundation) under Germany’s Excellence Strategy – EXC 2177/1 – Project ID 390895286.
PY - 2019/10
Y1 - 2019/10
N2 - The integration of application specific instruction set processors (ASIPs) in hearing aids requires various architectural customizations and software-side optimizations in order to meet the stringent power consumption constraints and processing performance demands. This paper presents the KAVUAKA application specific hearing aid processor and its ASIC integration as a system on chip (SoC). The final system contains four KAVUAKA processor cores and ten co-processors. Each of these processors and co-processors were individually customized and differ in their data path width. The processors are organized in two clusters, which share memories, an audio interface, co-processors and a serial interface. With this system, different hearing aid systems are evaluated in terms of performance, power and area by activating different processor and co-processor combinations. A 40 nm low power technology was used to build this research hearing aid system. The die size is 3.6 mm 2 with less than 1 mm 2 per core. The measured average power consumption is less than 1 mW per core.
AB - The integration of application specific instruction set processors (ASIPs) in hearing aids requires various architectural customizations and software-side optimizations in order to meet the stringent power consumption constraints and processing performance demands. This paper presents the KAVUAKA application specific hearing aid processor and its ASIC integration as a system on chip (SoC). The final system contains four KAVUAKA processor cores and ten co-processors. Each of these processors and co-processors were individually customized and differ in their data path width. The processors are organized in two clusters, which share memories, an audio interface, co-processors and a serial interface. With this system, different hearing aid systems are evaluated in terms of performance, power and area by activating different processor and co-processor combinations. A 40 nm low power technology was used to build this research hearing aid system. The die size is 3.6 mm 2 with less than 1 mm 2 per core. The measured average power consumption is less than 1 mW per core.
KW - asic
KW - asip
KW - hearing aid
KW - low-power
KW - processor
KW - system on chip
UR - http://www.scopus.com/inward/record.url?scp=85076823916&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2019.8920354
DO - 10.1109/VLSI-SoC.2019.8920354
M3 - Conference contribution
AN - SCOPUS:85076823916
SN - 978-1-7281-3916-6
T3 - International Conference on VLSI and System-on-Chip
SP - 99
EP - 104
BT - 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
A2 - Metzler, Carolina
A2 - De Micheli, Giovanni
A2 - Gaillardon, Pierre-Emmanuel
A2 - Silva-Cardenas, Carlos
A2 - Reis, Ricardo
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 6 October 2019 through 9 October 2019
ER -