Details
| Original language | English |
|---|---|
| Title of host publication | 2020 9th International Conference on Modern Circuits and Systems Technologies |
| Subtitle of host publication | MOCAST 2020 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (electronic) | 9781728166872 |
| Publication status | Published - 2020 |
| Event | 9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020 - Bremen, Germany Duration: 7 Sept 2020 → 9 Sept 2020 |
Abstract
Predication is a well-known alternative to conditional branching. However, the implementation of predication is costly in terms of extending the instruction set of the processor architecture. In this paper, a predication encoding technique for VLIW processors is proposed. Instead of using additional bits in the instruction encoding, the assigned issue-slot of a conditionally executed instruction encodes the associated predicate register. The number of addressable predicate registers scales with the number of issue-slots. All predicate registers have only one read and write port and can be accessed in parallel. Compared to the related work, no additional instruction encoding bits for selecting a predicate register are required and the processor core area increases only by about 1% per predicate register set. With the proposed predication technique, the processing performance increases by up to 4.5% when using two instead of one predicate register for a digital filter case study with floating-point emulation operations. A second case study shows, that conditional execution with two predicate register in combination with loop unrolling and operation merging almost doubles the achieved parallel instructions per cycle for a bit-reversal permutation algorithm.
Keywords
- conditional execution, predication, VLIW
ASJC Scopus subject areas
- Computer Science(all)
- Computer Networks and Communications
- Computer Science(all)
- Hardware and Architecture
- Energy(all)
- Energy Engineering and Power Technology
- Engineering(all)
- Electrical and Electronic Engineering
- Engineering(all)
- Safety, Risk, Reliability and Quality
- Mathematics(all)
- Control and Optimization
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2020 9th International Conference on Modern Circuits and Systems Technologies: MOCAST 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9200304.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Issue-Slot Based Predication Encoding Technique for VLIW Processors
AU - Gerlach, Lukas
AU - Stuckmann, Fabian
AU - Blume, Holger
AU - Paya-Vaya, Guillermo
N1 - Funding information: This work was funded by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Germany’s Excellence Strategy — EXC 2177/1 — Project ID 390895286.
PY - 2020
Y1 - 2020
N2 - Predication is a well-known alternative to conditional branching. However, the implementation of predication is costly in terms of extending the instruction set of the processor architecture. In this paper, a predication encoding technique for VLIW processors is proposed. Instead of using additional bits in the instruction encoding, the assigned issue-slot of a conditionally executed instruction encodes the associated predicate register. The number of addressable predicate registers scales with the number of issue-slots. All predicate registers have only one read and write port and can be accessed in parallel. Compared to the related work, no additional instruction encoding bits for selecting a predicate register are required and the processor core area increases only by about 1% per predicate register set. With the proposed predication technique, the processing performance increases by up to 4.5% when using two instead of one predicate register for a digital filter case study with floating-point emulation operations. A second case study shows, that conditional execution with two predicate register in combination with loop unrolling and operation merging almost doubles the achieved parallel instructions per cycle for a bit-reversal permutation algorithm.
AB - Predication is a well-known alternative to conditional branching. However, the implementation of predication is costly in terms of extending the instruction set of the processor architecture. In this paper, a predication encoding technique for VLIW processors is proposed. Instead of using additional bits in the instruction encoding, the assigned issue-slot of a conditionally executed instruction encodes the associated predicate register. The number of addressable predicate registers scales with the number of issue-slots. All predicate registers have only one read and write port and can be accessed in parallel. Compared to the related work, no additional instruction encoding bits for selecting a predicate register are required and the processor core area increases only by about 1% per predicate register set. With the proposed predication technique, the processing performance increases by up to 4.5% when using two instead of one predicate register for a digital filter case study with floating-point emulation operations. A second case study shows, that conditional execution with two predicate register in combination with loop unrolling and operation merging almost doubles the achieved parallel instructions per cycle for a bit-reversal permutation algorithm.
KW - conditional execution
KW - predication
KW - VLIW
UR - http://www.scopus.com/inward/record.url?scp=85093859311&partnerID=8YFLogxK
U2 - 10.1109/mocast49295.2020.9200304
DO - 10.1109/mocast49295.2020.9200304
M3 - Conference contribution
AN - SCOPUS:85093859311
BT - 2020 9th International Conference on Modern Circuits and Systems Technologies
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020
Y2 - 7 September 2020 through 9 September 2020
ER -