Details
| Original language | English |
|---|---|
| Pages (from-to) | 27-49 |
| Number of pages | 23 |
| Journal | Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology |
| Volume | 23 |
| Issue number | 1 |
| Publication status | Published - 1 Oct 1999 |
Abstract
This paper describes instruction set extensions for the acceleration of MPEG-4 algorithms on programmable (RISC-) CPUs. MPEG-4 standardizes audio and video compression schemes for a variety of bit rates and scenarios. As MPEG-4 targets a much broader range of different applications than previously defined hybrid video coding standards like H.263 or MPEG-2, it employs a much higher number of different algorithms and coding modes. Therefore, MPEG-4 implementations will require a more software-oriented approach to be efficient. However, the total computational load for an optimized implementation of an MPEG-4 video codec is expected to exceed the performance levels of today's multimedia signal processors, making further hardware acceleration a necessity. For that purpose, we propose a number of instruction set extensions that add function-specific blocks to the data path of a CPU. These dedicated modules are highly adapted to the most computation-intensive processing schemes of MPEG-4, such as DCT, motion compensation, padding, shape coding, or bitstream parsing. The increased functionality of basic instructions results in a significant speed-up over standard RISC instruction sets, thus making MPEG-4 implementations feasible on programmable processor platforms. Possible target architectures include VLIW multimedia processors, MIMD-style multiprocessors, or coprocessor architectures.
ASJC Scopus subject areas
- Computer Science(all)
- Signal Processing
- Computer Science(all)
- Information Systems
- Engineering(all)
- Electrical and Electronic Engineering
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In: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 23, No. 1, 01.10.1999, p. 27-49.
Research output: Contribution to journal › Article › Research › peer review
}
TY - JOUR
T1 - Instruction Set Extensions for MPEG-4 Video
AU - Berekovic, Mladen
AU - Stolberg, Hans Joachim
AU - Kulaczewski, Mark B.
AU - Pirsch, Peter
AU - Möller, Henning
AU - Runge, Holger
AU - Kneip, Johannes
AU - Stabernack, Benno
N1 - Funding Information: Parts of this work were sponsored by the European ACTS-105 Emphasis and Medea-M4M projects. The authors want to thank their colleagues from Emphasis and M4M for fruitful discussions about virtually all aspects of MPEG-4.
PY - 1999/10/1
Y1 - 1999/10/1
N2 - This paper describes instruction set extensions for the acceleration of MPEG-4 algorithms on programmable (RISC-) CPUs. MPEG-4 standardizes audio and video compression schemes for a variety of bit rates and scenarios. As MPEG-4 targets a much broader range of different applications than previously defined hybrid video coding standards like H.263 or MPEG-2, it employs a much higher number of different algorithms and coding modes. Therefore, MPEG-4 implementations will require a more software-oriented approach to be efficient. However, the total computational load for an optimized implementation of an MPEG-4 video codec is expected to exceed the performance levels of today's multimedia signal processors, making further hardware acceleration a necessity. For that purpose, we propose a number of instruction set extensions that add function-specific blocks to the data path of a CPU. These dedicated modules are highly adapted to the most computation-intensive processing schemes of MPEG-4, such as DCT, motion compensation, padding, shape coding, or bitstream parsing. The increased functionality of basic instructions results in a significant speed-up over standard RISC instruction sets, thus making MPEG-4 implementations feasible on programmable processor platforms. Possible target architectures include VLIW multimedia processors, MIMD-style multiprocessors, or coprocessor architectures.
AB - This paper describes instruction set extensions for the acceleration of MPEG-4 algorithms on programmable (RISC-) CPUs. MPEG-4 standardizes audio and video compression schemes for a variety of bit rates and scenarios. As MPEG-4 targets a much broader range of different applications than previously defined hybrid video coding standards like H.263 or MPEG-2, it employs a much higher number of different algorithms and coding modes. Therefore, MPEG-4 implementations will require a more software-oriented approach to be efficient. However, the total computational load for an optimized implementation of an MPEG-4 video codec is expected to exceed the performance levels of today's multimedia signal processors, making further hardware acceleration a necessity. For that purpose, we propose a number of instruction set extensions that add function-specific blocks to the data path of a CPU. These dedicated modules are highly adapted to the most computation-intensive processing schemes of MPEG-4, such as DCT, motion compensation, padding, shape coding, or bitstream parsing. The increased functionality of basic instructions results in a significant speed-up over standard RISC instruction sets, thus making MPEG-4 implementations feasible on programmable processor platforms. Possible target architectures include VLIW multimedia processors, MIMD-style multiprocessors, or coprocessor architectures.
UR - http://www.scopus.com/inward/record.url?scp=0033207374&partnerID=8YFLogxK
U2 - 10.1023/A:1008188618930
DO - 10.1023/A:1008188618930
M3 - Article
AN - SCOPUS:0033207374
VL - 23
SP - 27
EP - 49
JO - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
JF - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
SN - 0922-5773
IS - 1
ER -