Details
| Original language | English |
|---|---|
| Title of host publication | 2009 International Symposium on System-on-Chip - Proceedings, SoC 2009 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 143-146 |
| Number of pages | 4 |
| ISBN (print) | 9781424444670 |
| Publication status | Published - 13 Nov 2009 |
| Event | 2009 International Symposium on System-on-Chip, SoC 2009 - Tampere, Finland Duration: 5 Oct 2009 → 7 Oct 2009 |
Abstract
This paper describes a new mechanism for concurrent use of more functional units, without increasing the control path of a generic VLIW architecture. The proposed approach only requires small modifications in the architecture and a new code selection function in the instruction scheduler. The key idea of this approach is to search for similar independent operations inside a basic assembler code block and merge them in a single instruction, which executes the same operation with even and odd operand registers in two different functional units. A comprehensive evaluation of this mechanism with two multimedia tasks shows an improvement of the dynamic instructions-per-cycle, exceeding the theoretical maximum of the reference architecture.
ASJC Scopus subject areas
- Computer Science(all)
- Hardware and Architecture
- Engineering(all)
- Control and Systems Engineering
- Engineering(all)
- Electrical and Electronic Engineering
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2009 International Symposium on System-on-Chip - Proceedings, SoC 2009. Institute of Electrical and Electronics Engineers Inc., 2009. p. 143-146 5335660.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Instruction merging to increase parallelism in VLIW architectures
AU - Payá-Vayá, Guillermo
AU - Martín-Langerwerf, Javier
AU - Giesemann, Florian
AU - Blume, Holger
AU - Pirsch, Peter
PY - 2009/11/13
Y1 - 2009/11/13
N2 - This paper describes a new mechanism for concurrent use of more functional units, without increasing the control path of a generic VLIW architecture. The proposed approach only requires small modifications in the architecture and a new code selection function in the instruction scheduler. The key idea of this approach is to search for similar independent operations inside a basic assembler code block and merge them in a single instruction, which executes the same operation with even and odd operand registers in two different functional units. A comprehensive evaluation of this mechanism with two multimedia tasks shows an improvement of the dynamic instructions-per-cycle, exceeding the theoretical maximum of the reference architecture.
AB - This paper describes a new mechanism for concurrent use of more functional units, without increasing the control path of a generic VLIW architecture. The proposed approach only requires small modifications in the architecture and a new code selection function in the instruction scheduler. The key idea of this approach is to search for similar independent operations inside a basic assembler code block and merge them in a single instruction, which executes the same operation with even and odd operand registers in two different functional units. A comprehensive evaluation of this mechanism with two multimedia tasks shows an improvement of the dynamic instructions-per-cycle, exceeding the theoretical maximum of the reference architecture.
UR - http://www.scopus.com/inward/record.url?scp=74549145102&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2009.5335660
DO - 10.1109/SOCC.2009.5335660
M3 - Conference contribution
AN - SCOPUS:74549145102
SN - 9781424444670
SP - 143
EP - 146
BT - 2009 International Symposium on System-on-Chip - Proceedings, SoC 2009
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2009 International Symposium on System-on-Chip, SoC 2009
Y2 - 5 October 2009 through 7 October 2009
ER -