Details
| Original language | English |
|---|---|
| Title of host publication | NEIS 2020 |
| Subtitle of host publication | Conference on Sustainable Energy Supply and Energy Storage Systems |
| Publisher | VDE Verlag GmbH |
| Pages | 93-98 |
| Number of pages | 6 |
| ISBN (print) | 978-3-8007-5359-8 |
| Publication status | Published - 2020 |
| Event | NEIS 2020: 8th Conference on Sustainable Energy Supply and Energy Storage Systems - Hamburg, Germany Duration: 14 Sept 2020 → 15 Sept 2020 |
Abstract
Within this paper, an improved PLL structure that combines both synchronous reference frame PLL (SRF-PLL) and decoupled double synchronous reference frame PLL (DDSRF-PLL) is presented. This hybrid DDSRF-PLL (HDDSRF-PLL) improves the positive sequence component tracking and leads to a better current response of the converter during transients compared to DDSRF-PLL. In the HDDSRF-PLL the positive sequence component is estimated by a SRF-PLL. The input signal of the SRF-PLL is reduced by the negative sequence component estimated by a DDSRF-PLL. Thus, the delays associated with sequence separation in positive sequence reference frame are avoided. The dynamic performance of the HDDSRF-PLL is validated with voltage drops caused by symmetrical and unsymmetrical short-circuits. The performance of the HDDSRF-PLL is compared with the performance of the DDSRF-PLL.
Keywords
- Decoupled double synchronous reference frame (DDSRF), Fault ride through (FRT), Grid-connected converter, Phase locked loop (PLL), Synchronization
ASJC Scopus subject areas
Sustainable Development Goals
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NEIS 2020: Conference on Sustainable Energy Supply and Energy Storage Systems. VDE Verlag GmbH, 2020. p. 93-98.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
}
TY - GEN
T1 - Hybrid PLL Structure for Improvement of the Dynamic Performance of Grid-Connected Converters
AU - Schäkel, N.
AU - Neufeld, A.
AU - Hofmann, L.
PY - 2020
Y1 - 2020
N2 - Within this paper, an improved PLL structure that combines both synchronous reference frame PLL (SRF-PLL) and decoupled double synchronous reference frame PLL (DDSRF-PLL) is presented. This hybrid DDSRF-PLL (HDDSRF-PLL) improves the positive sequence component tracking and leads to a better current response of the converter during transients compared to DDSRF-PLL. In the HDDSRF-PLL the positive sequence component is estimated by a SRF-PLL. The input signal of the SRF-PLL is reduced by the negative sequence component estimated by a DDSRF-PLL. Thus, the delays associated with sequence separation in positive sequence reference frame are avoided. The dynamic performance of the HDDSRF-PLL is validated with voltage drops caused by symmetrical and unsymmetrical short-circuits. The performance of the HDDSRF-PLL is compared with the performance of the DDSRF-PLL.
AB - Within this paper, an improved PLL structure that combines both synchronous reference frame PLL (SRF-PLL) and decoupled double synchronous reference frame PLL (DDSRF-PLL) is presented. This hybrid DDSRF-PLL (HDDSRF-PLL) improves the positive sequence component tracking and leads to a better current response of the converter during transients compared to DDSRF-PLL. In the HDDSRF-PLL the positive sequence component is estimated by a SRF-PLL. The input signal of the SRF-PLL is reduced by the negative sequence component estimated by a DDSRF-PLL. Thus, the delays associated with sequence separation in positive sequence reference frame are avoided. The dynamic performance of the HDDSRF-PLL is validated with voltage drops caused by symmetrical and unsymmetrical short-circuits. The performance of the HDDSRF-PLL is compared with the performance of the DDSRF-PLL.
KW - Decoupled double synchronous reference frame (DDSRF)
KW - Fault ride through (FRT)
KW - Grid-connected converter
KW - Phase locked loop (PLL)
KW - Synchronization
UR - http://www.scopus.com/inward/record.url?scp=85098641945&partnerID=8YFLogxK
M3 - Conference contribution
SN - 978-3-8007-5359-8
SP - 93
EP - 98
BT - NEIS 2020
PB - VDE Verlag GmbH
T2 - NEIS 2020
Y2 - 14 September 2020 through 15 September 2020
ER -